Patent US4037162A successfully refreshed from Google Patents.
US4037162A
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Pseudo sampling
Assignee: United States Department of the Navy
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Filing: 1975-05-27
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Granted: 1977-07-19
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Expires: 1995-05-27
Abstract
Abstract A technique for effectively sampling continuous signals including signals of rapid, sharp pulses, by interrogating discrete portions of the signal through integration rather than by conventional samples.
Inventors
- 👤 Jon H. Bumgardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:44
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
152 words
In a system for sampling an electrical signal as a means for interrogating it, the improvement of pseudo-sampling said signal by sampling the value of it at discrete portions of finite width instead of instantaneously sampling said signal at discrete portions of infinitely narrow width, and by compensating the sampled value with an attenuation figure to obtain the true signal value comprising; means for sampling the value of said signal wherein the sample period is of finite duration, and providing a separate result for each portion sampled; means for modifying each said result by compensating for relative attenuation induced by the utilization of said sample means, wherein said relative attenuation is given by α(f) = 2 sin (f π/2)/πf, and wherein f is twice the frequency of the signal sampled times the duration of the sample period; such that the modified results can be investigated as a means for interrogating said signal.
Claim 2
Dependent Claim
152 words
In a system for sampling an electrical signal as a means for interrogating it, the improvement of pseudo-sampling said signal by sampling the value of it at discrete portions of finite width instead of instantaneously sampling said signal at discrete portions of infinitely narrow width, and by compensating the sampled value with an attenuation figure to obtain the true signal value comprising; means for sampling the value of said signal wherein the sample period is of finite duration, and providing a separate result for each portion sampled; means for modifying each said result by compensating for relative attenuation induced by the utilization of said sample means, wherein said relative attenuation is given by α(f) = 2 sin (f π/2)/πf, and wherein f is twice the frequency of the signal sampled times the duration of the sample period; such that the modified results can be investigated as a means for interrogating said signal.
Claim 3
Dependent Claim
31 words
The system of claim 1 wherein said sampling and providing means includes electronic means for selectively enabling said sampling means such that successive, discrete portions of said signal are separately integrated.
Claim 4
Dependent Claim
65 words
The system of claim 2 wherein said sampling and providing means further includes means for providing first and second currents paths for said signal, wherein said first path is normally conductive and prevents sampling of portions conducted thereby, and said second path is normally non-conductive and rendered conductive by an output from said sampling enabling means which disables said first path and renders it non-conductive.
Claim 5
Dependent Claim
53 words
The system of claim 3 wherein said sampling and providing means further includes a bank of storage means coupled to said second path for integrating that which is conducted by said second path, and providing the result as an output value wherein each of said storage means is selectively and separately enabled electrically.
Claim 6
Dependent Claim
28 words
The system of claim 4 wherein a separate transistor is electrically in series with each storage means for enabling said storage means when said transistor is rendered conductive.
Claim 7
Dependent Claim
40 words
The system of claim 5 wherein said means for selectively enabling said sampling and providing means is a MECL III logic line coupled to said first current path for disabling said first path when said MECL III provides an output.
Claim 8
Dependent Claim
23 words
The system of claim 6 wherein said means for providing first and second current paths is a differential amplifier employing a 2N4261 transistor.
Claim 9
Dependent Claim
31 words
The system of claim 7 wherein said bank of storage means is a bank of identical capacitors, and the separate transistors in series with each capacitor are identical field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |