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US4036706A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for providing electrical isolation between spaced portions of a layer of semiconductive material and the product produced thereby

Assignee: International Telephone and Telegraph Corp
•
Filing: 1976-03-25
•
Granted: 1977-07-19
•
Expires: 1996-03-25
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Abstract

Abstract A semiconductor device has a plurality of electronic elements formed in spaced portions of a layer of semiconductive material which is disposed on a substrate. Electrical isolation is provided between the spaced portions by a layer of dielectric material formed on the peripheral surfaces of the spaced portions and on the substrate. Metal is disposed on the dielectric layer in said spaces for filling the spaces and providing a planar surface. The isolation is provided by forming a dielectric layer over the surface of the semiconductor device and thereafter removing the dielectric and the semiconductive material of the layer in regions between the portions of the layer in which the elements are formed to expose the substrate. A dielectric layer is then formed on the exposed substrate and the peripheral surfaces of the spaced portions. A metal is deposited onto the semiconductor device so that metal layers are formed on the substrate dielectric and on the surface dielectric, said metal layers being electrically isolated from each other. The metal layer on the substrate dielectric is electrolytically treated to change its surface characteristics after which the untreated metal on the surface dielectric is etched using a compound that attacks the untreated metal but has little or no effect on the treated metal on the substrate dielectric. Additional metal is plated onto the metal on the substrate dielectric to fill the entire space and provide a planar surface.

Inventors

  • 👤 Raymond E. Scherrer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; C; C25; C25D; C25D7/00; C25D7/12; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0142; H10W10/10; H10W10/17; H10W20/021; H10W20/031; H10W20/056; H10W20/057; H10W20/064; H10W20/065

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 146 words
A method for providing electrical isolation in semiconductive material while maintaining a planar surface, comprising the steps of: removing the semiconductive material from regions of a planar surface in which isolation is desired to form an isolation moat; forming a dielectric layer on the surfaces of the semiconductive material defining the moat; depositing a metal over the semiconductive material so that the metal covers the planar surface of the semiconductive material and only a portion of the surfaces defining the isolation moat; forming a protective layer over the metal deposited in the isolation moat; selectively removing the metal deposited on the planar surface of the semiconductive material using an etchant that attacks said metal but has little or no effect on the protective layer; and selectively plating metal into the isolation moat to substantially fill said moat and provide a planar surface with the semiconductive material.
Claim 2
Independent Claim 146 words
A method for providing electrical isolation in semiconductive material while maintaining a planar surface, comprising the steps of: removing the semiconductive material from regions of a planar surface in which isolation is desired to form an isolation moat; forming a dielectric layer on the surfaces of the semiconductive material defining the moat; depositing a metal over the semiconductive material so that the metal covers the planar surface of the semiconductive material and only a portion of the surfaces defining the isolation moat; forming a protective layer over the metal deposited in the isolation moat; selectively removing the metal deposited on the planar surface of the semiconductive material using an etchant that attacks said metal but has little or no effect on the protective layer; and selectively plating metal into the isolation moat to substantially fill said moat and provide a planar surface with the semiconductive material.
Claim 3
Dependent Claim 60 words
A method as described in claim 1, wherein the step of forming a protective layer over the metal deposited in the isolation moat comprises the step of electrolytically treating the deposited metal in the isolation moat to modify the surface characteristics of said metal so that it may be distinguished from the metal on the surface of the semiconductive material.
Claim 4
Dependent Claim 36 words
A method as described in claim 2, wherein the electrolytic treating of the metal in the isolation regions comprises the step of anodizing a portion of said metal so that it has a different surface characteristic.
Claim 5
Dependent Claim 48 words
A method as described in claim 2, wherein the step of electrolytically treating comprises the step of plating a different metal onto the surface of the deposited metal, said plated metal having different characteristics than the deposited metal so that it will not be attacked by the etch.
Claim 6
Dependent Claim 38 words
A method as described in claim 2, wherein the electrolytically treated portion of the metal is removed from the isolation region after the surface metal is removed and thereafter the plated metal is applied to the deposited metal.
Claim 7
Dependent Claim 61 words
A method as described in claim 2, wherein the deposited metal in the isolation regions is anodized to provide a layer of anodized metal on the surface of the deposited metal and the unanodized metal on the surface of the semiconductive material is removed by etching in a solution that does not attack the anodized metal but removes the unanodized metal.
Claim 8
Dependent Claim 34 words
A method as described in claim 6, additionally comprising the step of removing the anodized metal from the isolation region and thereafter plating the additional metal layers onto the surface of the deposited metal.
Claim 9
Dependent Claim 33 words
A method as described in claim 1, wherein the step of depositing a metal comprises the step of depositing a first metal over the seimconductive material and thereafter depositing a second metal thereon.
Claim 10
Dependent Claim 60 words
A method as described in claim 8, wherein a layer of plated metal is formed on the second layer of deposited metal in the isolation regions and thereafter the layers of deposited metal on the surface of the semiconductive material are removed using an etch that attacks the deposited metal but has little or no effect on the plated metal.
Claim 11
Dependent Claim 29 words
A method as described in claim 9, wherein additional metal is plated onto the plated metal after the deposited metal is etched from the surface of the semiconductive material.

References Cited (Backward Citations)

US3912556A Cited
US3968565A Cited
US3950233A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-07-18 1981-01-17 1981-07-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-07-18 1985-01-17 1985-07-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-07-18 1989-01-17 1989-07-19 $7700.00 Window Closed / Lapsed

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