Patent US4034467A successfully refreshed from Google Patents.
US4034467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for producing a multi-chip wiring arrangement
Assignee: Siemens AG
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Filing: 1975-09-02
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Granted: 1977-07-12
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Expires: 1995-09-02
Abstract
Abstract A process for producing multi-chip wiring which facilitates high packing density and reliable flip-chip connections. In the process, an adhesive layer and a contact layer are vapor deposited onto a carrier. The desired structure of the connector path, outer contacts and connection surfaces are covered with a conductive layer and an intermediate layer with the aid of a first photo-lacquer mask by galvanic metal deposition. A solder-rejecting layer is galvanically deposited onto the structure of the conductor paths with the aid of a second photo-lacquer mask. The undesired regions of the adhesive layer and of the contact layer are etched away and the outer contacts and connection surfaces are covered with a solderable contact layer by selective currentless metal deposition.
Inventors
- 👤 Michail Sapunarow
- 👤 Wolfgang Bade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:55
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H05K3/22; H05K3/24; H05K3/243; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0367; H05K2201/20; H05K2201/2081; H05K2203/00; H05K2203/07; H05K2203/0703; H05K2203/072; H05K3/02; H05K3/06; H05K3/061; H05K3/062; H05K3/10; H05K3/108; H05K3/38; H05K3/388; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49158
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A method for producing a multi-chip wiring arrangement having outer contacts for subsequent wiring and connection surfaces for being soldered to semiconductor modules in the flip-chip technique on an insulation carrier comprising the steps of: obtaining a suitable carrier layer, applying an adhesive layer and then a contacting layer onto a surface of the carrier, applying a photo mask to the surface of the contacting layer to leave outer contacts, connection surfaces and conductor paths exposed while masking other areas, metal depositing a conductive layer onto exposed areas of said contacting layer through said photo mask, metal depositing an intermediate layer onto said conductive layer, applying a second photo mask onto said intermediate layer to leave exposed the areas corresponding to said conductor paths, depositing a solder rejecting layer onto said conductor paths through said second photo mask, etching away the undesired regions of the adhesive layer and contacting layer, and covering the outer contacts and connection surfaces with a solderable contact layer.
Claim 2
Independent Claim
163 words
A method for producing a multi-chip wiring arrangement having outer contacts for subsequent wiring and connection surfaces for being soldered to semiconductor modules in the flip-chip technique on an insulation carrier comprising the steps of: obtaining a suitable carrier layer, applying an adhesive layer and then a contacting layer onto a surface of the carrier, applying a photo mask to the surface of the contacting layer to leave outer contacts, connection surfaces and conductor paths exposed while masking other areas, metal depositing a conductive layer onto exposed areas of said contacting layer through said photo mask, metal depositing an intermediate layer onto said conductive layer, applying a second photo mask onto said intermediate layer to leave exposed the areas corresponding to said conductor paths, depositing a solder rejecting layer onto said conductor paths through said second photo mask, etching away the undesired regions of the adhesive layer and contacting layer, and covering the outer contacts and connection surfaces with a solderable contact layer.
Claim 3
Dependent Claim
31 words
A method in accordance with claim 1, wherein said first named photo mask is a photo-lacquer mask and wherein said conductive layer and intermediate layer are applied by galvanic metal deposition.
Claim 4
Dependent Claim
19 words
A method in accordance with claim 1, wherein said adhesive layer and contacting layer are applied by vapor deposition.
Claim 5
Dependent Claim
19 words
A method in accordance with claim 1, wherein said adhesive layer and contacting layer are sputtered onto the carrier.
Claim 6
Dependent Claim
26 words
A method in accordance with claim 1, wherein said solderable contact layer is applied to the outer contacts and connection surfaces by selective currentless metal deposition.
Claim 7
Dependent Claim
23 words
A method in accordance with claim 1, wherein said adhesive layer is formed from titanium and the contacting layer is formed from copper.
Claim 8
Dependent Claim
27 words
A method in accordance with claim 1, wherein the conductive layer consists of copper, the intermediate layer consists of nickel and the solder-rejecting layer consists of chrome.
Claim 9
Dependent Claim
28 words
A method in accordance with claim 1, wherein the solderable contact layer is selectively deposited in a currentless gold bath operating by the ion-exchange principle, without previous masking.
Claim 10
Dependent Claim
28 words
A method in accordance with claim 1, including the step of dipping the solderable contact layers in a solder bath to form solder layers on the surface thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |