Interconnection means for an array of majority carrier microwave devices

Claim 2

In a majority carrier transistor array comprising a plurality of integrated field effect transistors situated on a substrate wherein each transistor comprises a source and a drain separated by a channel, a source contact connected to the source, a drain pad connected to the drain, and a gate pad connected to the channel, and wherein each of the gate pads is situated adjacent a common edge of the substrate and each of the drain pads is situated adjacent another common edge, the array further comprising means for connecting each of the gate pads to a first conductive member and means for connecting each of the drain pads to a second conductive member, the improvement wherein the means for connecting each of the gate pads comprises at least ONE bilaterally symmetric first quadrangular conductive member SYMMETRICALLY interconnecting a PLURALITY of gate pads to the first conductive member, each of the gate pads being connected adjacent a COMMON EDGE of the first member, and the improvement wherein the means for connecting each of the drain pads comprises at least ONE second bilaterally symmetric conductive quadrangular member SYMMETRICALLY connecting a plurality of drain pads to the second conductive member, each of the drain pads being connected adjacent a COMMON edge of the second member.

Claim 3

The array of claim 1, wherein said first and second quadrangular conductive members are substantially rectangles.

Claim 4

In a microwave field effect transistor array comprising a plurality of field effect transistors integrally situated on a substrate wherein each transistor has a gate, a source, and a drain, the gate located between the source and the drain and wherein each transistor has a gate pad connected to the gate and a drain pad connected to the drain, the array further comprising means for connecting each of the gate pads to a first bus on a substrate carrier and means for connecting each of the drain pads to a second bus on the carrier, the improvement wherein the means for connecting each of the gate pads comprises at least one first bilaterally symmetric quadrangular conductive member symmetrically interconnecting a plurality of gate pads to the first bus.

Claim 5

In a microwave field effect transistor array comprising a plurality of field effect transistors integrally situated on a substrate wherein each transistor has a gate, a source, and a drain, the gate located between the source and the drain and wherein each transistor has a gate pad connected to the gate and a drain pad connected to the drain, the array further comprising means for connecting each of the gate pads to a first bus on a substrate carrier and means for connecting each of the drain pads to a second bus on the carrier, the improvement wherein the means for connecting each of the gate pads comprises at least one first bilaterally symmetric quadrangular conductive member symmetrically interconnecting a plurality of gate pads to the first bus.

Claim 6

The array of claim 3 further comprising the improvement wherein the means for connecting each of the drain pads comprises at least one second rectangular conductive member interconnecting a plurality of drain pads to the second bus.

Claim 7

The array of claim 4 wherein each of the gate pads is situated adjacent a common edge of the substrate and each of the drain pads is situated adjacent another common edge of the substrate, and wherein each of the gate pads is connected adjacent a common edge of the first member, an opposite edge of the first member being connected to the first bus and wherein each of the drain pads is connected adjacent a common edge of the second member, an opposite edge of the second member being connected to the second bus.

Claim 8

The array of claim 5 wherein each rectangular conductive member is comprised of metal.

Claim 9

The array of claim 6 wherein the source of each transistor is relatively taller with respect to the drains and gates and each source is of approximately the same height.

Claim 10

In combination, a microwave field effect transistor array comprising a plurality of field effect transistors situated on a substrate wherein each transistor has a gate, a source, and a drain and wherein each transistor has a gate pad and a drain pad, and wherein each of the gate pads is situated adjacent a common edge of the substrate and each of the drain pads is situated adjacent another common edge, the array further comprising means for connecting each of the gate pads to a first bus on a substrate carrier and means for connecting each of the drain pads to a second bus on the carrier, wherein the means for connecting each of the gate pads comprises at least one rectangular first conductive member interconnecting a plurality of gate pads to the first bus, each of the gate pads being connected adjacent a common edge of the first member, an opposite edge of the first member being connected to the first bus and wherein the means for connecting each of the drain pads comprises at least one second rectangular conductive member interconnecting a plurality of drain pads to the second bus, each of the drain pads being connected adjacent a common edge of the second member, an opposite edge of the second member being connected to the second bus, the substrate carrier comprising a conductive base, the two conductive busses being located on a major surface of the base at opposite edges thereof, the sources of the array being connected to the major surface such that the substrate is inverted inside the carrier in flip chip fashion.

Claim 11

In combination, a microwave field effect transistor array comprising a plurality of field effect transistors situated on a substrate wherein each transistor has a gate, a source, and a drain and wherein each transistor has a gate pad and a drain pad, and wherein each of the gate pads is situated adjacent a common edge of the substrate and each of the drain pads is situated adjacent another common edge, the array further comprising means for connecting each of the gate pads to a first bus on a substrate carrier and means for connecting each of the drain pads to a second bus on the carrier, wherein the means for connecting each of the gate pads comprises at least one rectangular first conductive member interconnecting a plurality of gate pads to the first bus, each of the gate pads being connected adjacent a common edge of the first member, an opposite edge of the first member being connected to the first bus and wherein the means for connecting each of the drain pads comprises at least one second rectangular conductive member interconnecting a plurality of drain pads to the second bus, each of the drain pads being connected adjacent a common edge of the second member, an opposite edge of the second member being connected to the second bus, the substrate carrier comprising a conductive base, the two conductive busses being located on a major surface of the base at opposite edges thereof, the sources of the array being connected to the major surface such that the substrate is inverted inside the carrier in flip chip fashion.

Claim 12

A means for interconnecting a plurality of like pads of an array of radio frequency devices to a bus comprising a rectangular flat conductive member, said member having at least four edges, said member being connected along a first edge of the member to a selected plurality of the pads, an opposite edge of the member being connected to the bus, each said device being comprised of a semiconductor substrate, the substrate comprising a source, a drain, a channel separating the source from the drain, said device further comprising a gate pad connected to the channel and a drain pad connected to the drain, and said member being bilaterally symmetric about a central bisector transverse to the first edge.

Claim 13

A means for interconnecting a plurality of like pads of an array of radio frequency devices to a bus comprising a rectangular flat conductive member, said member having at least four edges, said member being connected along a first edge of the member to a selected plurality of the pads, an opposite edge of the member being connected to the bus, each said device being comprised of a semiconductor substrate, the substrate comprising a source, a drain, a channel separating the source from the drain, said device further comprising a gate pad connected to the channel and a drain pad connected to the drain, and said member being bilaterally symmetric about a central bisector transverse to the first edge.

Claim 14

The means of claim 9, wherein the member has at least two digitated submembers formed at the first edge of the member, each of the submembers having a major surface, each of the submembers being connected at the entire major surface to a different pad of the selected plurality of pads.