Test apparatus and method

Claim 2

Apparatus comprising: a test input means for receiving serial binary data; a test output means for transmitting serial binary data; means for establishing a preselected binary test message representative of a computer command; means for serially transmitting said test message from said test output means; means for generating a first error code in response to transmission of said test message; means for transmitting said first error code from said test output means; means for receiving and storing a serial binary message response received by said test input means; and means for displaying said message response.

Claim 3

Apparatus in accordance with claim 2 additionally comprising: means for generating a second error code in response to said message response received by said test input means; means for comparing said second error code to a third error code received by said test input means following receipt of said message response and generating an error signal in response to said third error code being different from said second error code; and means for establishing an error signal alarm in response to said error signal.

Claim 4

Apparatus in accordance with claim 2 additionally comprising a remote unit means, said remote unit means comprising: means for receiving said test message and for generating and transmitting said message response in response to said test message; means for generating a fourth error code in response to said test message; means for comparing said first error code and said fourth error code and generating a remote error signal in response to said fourth error code being different from said first error code; and means for generating said third error code in response to transmission of said message response and for transmitting said third error code.

Claim 5

Apparatus comprising: a test input means for receiving serial binary data; a test output means for transmitting serial binary data; means for establishing a preselected binary test message representative of a computer command; means for serially transmitting said test message from said test output means; remote unit means for receiving said test message and generating a serial binary message response in response to said test message; means for receiving and storing said message response received by said test input means; and means for displaying said message response.

Claim 6

Apparatus comprising: a test input means for receiving serial binary data; a test output means for transmitting serial binary data; means for establishing a preselected binary test message representative of a computer command; means for serially transmitting said test message from said test output means; remote unit means for receiving said test message and generating a serial binary message response in response to said test message; means for receiving and storing said message response received by said test input means; and means for displaying said message response.

Claim 7

Apparatus comprising: a test input means for receiving serial binary data; a test output means for transmitting serial binary data; means for establishing a preselected binary test message representative of a computer command; means for serially transmitting said test message from said test output means; means for receiving a serial binary message response received by said test input means and for storing each binary data bit of said message response in a separate binary data storage location; and means for displaying said message response; wherein said means for transmitting said test message and said means for receiving and storing said message response comprise a first shift register means for accepting said test message and serially shifting said test message to said test output means and for receiving a serial message response from said test input means and shifting said message response into the data locations of said first shift register means.

Claim 8

Apparatus comprising: a test input means for receiving serial binary data; a test output means for transmitting serial binary data; means for establishing a preselected binary test message representative of a computer command; means for serially transmitting said test message from said test output means; means for receiving a serial binary message response received by said test input means and for storing each binary data bit of said message response in a separate binary data storage location; and means for displaying said message response; wherein said means for transmitting said test message and said means for receiving and storing said message response comprise a first shift register means for accepting said test message and serially shifting said test message to said test output means and for receiving a serial message response from said test input means and shifting said message response into the data locations of said first shift register means.

Claim 9

Apparatus in accordance with claim 5 additionally comprising first detector means for detecting receipt of a message response by said first shift register means and inhibiting further shifting of said first shift register in response thereto.

Claim 10

Apparatus in accordance with claim 6 additionally comprising a second shift register means for receiving said test message shifted from said first shift register to said test output means and for counting data bits received by said test input means following the operation of said first detector means to inhibit further shifting of said first shift register.

Claim 11

Apparatus in accordance with claim 7 additionally comprising second detector means for detecting the receipt by said second shift register of said test message and producing a second detector signal in response thereto, and third detector means for detecting the count by said second shift register means of a predetermined number of data bits received by said test input means following said operation of said first detector means and producing a third detector signal in response thereto.

Claim 12

Apparatus in accordance with claim 8 additionally comprising an error code generator means for generating a first error code in response to said test message shifted from said first shift register to said test output means and for generating a second error code in response to said message response received by said test input means; means responsive to said second detector signal for transmitting said first error code from said test output means; and means responsive to said third detector signal for comparing said second error code with a third error code received at said test input means.

Claim 13

Test apparatus having a test input means and a test output means, said apparatus comprising: a first shift register means having a plurality of data bit locations, a serial input means for receiving serial binary data, a serial output means for delivering serial binary data, a parallel input means associated with each said data bit location for receiving parallel data, and a parallel output means associated with each said data bit location for delivering parallel data; a switch means associated with each said parallel input means for providing a binary data bit thereto; a display means associated with each said parallel output means for displaying the content of the associated data bit location; an error code generating means having a serial input means and a serial output means for receiving a serial binary data message and delivering a serial binary error code in response thereto; a second shift register means having a serial input means for receiving serial binary data, a serial output means for delivering serial binary data, a first intermediate output means for delivering a signal responsive to receipt of said data message having a first predetermined length and a second intermediate output means for delivering a signal responsive to the receipt of an error code of a second predetermined length; first switch means responsive to said first intermediate output means of said second shift register means for operably connecting the serial input means of said second shift register means and said test output means to the serial output means of said first shift register means prior to receipt of said data message by said second shift register means and for operably connecting the serial input means of said second shift register and said test output means to the serial output means of said error code generating means following receipt of said data message by said second shift register means; second switch means for operably connecting the serial input means of said first shift register means to said test input means when said second switch means is in a first condition and for operably connecting the serial input means of said first shift register means to the serial output means of said second shift register means when said second switch means is in a second condition; third switch means for automatically operably connecting the serial input means of said error code generating means to the serial output means of said first shift register means when a data message is being serially shifted out of said first shift register means, and for automatically operably connecting the serial input means of said error code generating means to the serial input means of said first shift register means when a data message is being serially shifted into said first shift register means; an error detector means having a first serial input means operably connected to the serial input means of said first shift register means, a second serial input means operably connected to the serial output means of said error code generator means, and an error signal output means, for comparing two error codes delivered to the two serial input means thereof and delivering an error signal from the output means thereof in response to a difference between the two received error codes.

Claim 14

Test apparatus having a test input means and a test output means, said apparatus comprising: a first shift register means having a plurality of data bit locations, a serial input means for receiving serial binary data, a serial output means for delivering serial binary data, a parallel input means associated with each said data bit location for receiving parallel data, and a parallel output means associated with each said data bit location for delivering parallel data; a switch means associated with each said parallel input means for providing a binary data bit thereto; a display means associated with each said parallel output means for displaying the content of the associated data bit location; an error code generating means having a serial input means and a serial output means for receiving a serial binary data message and delivering a serial binary error code in response thereto; a second shift register means having a serial input means for receiving serial binary data, a serial output means for delivering serial binary data, a first intermediate output means for delivering a signal responsive to receipt of said data message having a first predetermined length and a second intermediate output means for delivering a signal responsive to the receipt of an error code of a second predetermined length; first switch means responsive to said first intermediate output means of said second shift register means for operably connecting the serial input means of said second shift register means and said test output means to the serial output means of said first shift register means prior to receipt of said data message by said second shift register means and for operably connecting the serial input means of said second shift register and said test output means to the serial output means of said error code generating means following receipt of said data message by said second shift register means; second switch means for operably connecting the serial input means of said first shift register means to said test input means when said second switch means is in a first condition and for operably connecting the serial input means of said first shift register means to the serial output means of said second shift register means when said second switch means is in a second condition; third switch means for automatically operably connecting the serial input means of said error code generating means to the serial output means of said first shift register means when a data message is being serially shifted out of said first shift register means, and for automatically operably connecting the serial input means of said error code generating means to the serial input means of said first shift register means when a data message is being serially shifted into said first shift register means; an error detector means having a first serial input means operably connected to the serial input means of said first shift register means, a second serial input means operably connected to the serial output means of said error code generator means, and an error signal output means, for comparing two error codes delivered to the two serial input means thereof and delivering an error signal from the output means thereof in response to a difference between the two received error codes.

Claim 15

Apparatus in accordance with claim 10 additionally comprising means for selecting among a plurality of rates at which serial data is shifted into and out of said first shift register, said error code generating means, said second shift register means and said error code detector means.

Claim 20

A method in accordance with claim 13 additionally comprising: serially shifting said test message from said first shift register to a second shift register; serially shifting said test message from said second shift register into said first shift register; stopping said first shift register upon receipt of said test message; and displaying said test message at a point in time adjacent the said steps of sending a test signal, receiving and storing a message response, and displaying said message response.

Claim 21

A method in accordance with claim 13 additionally comprising: generating a first error code in response to the shifting of said test message from first shift register; serially shifting said first error code to the input of said remote unit; generating a second error code in response to the shifting of said response from said remote unit into said first shift register; comparing said second error code to a third error code transmitted at the end of said message response from said remote unit; and generating an error signal if said second error code and said third error code differ.

Claim 22

A method in accordance with claim 13 comprising automatically retransmitting said test message from said first shift register means to said remote unit following receipt by said first shift register means of said response from said remote unit.