Time correction circuits for electronic timepieces

Claim 2

A time correction circuit for an electronic timepiece comprising a switch; a first shift register circuit including a plurality of cascade connected shift registers which are driven by a clock pulse having a first predetermined frequency for shifting an electric signal produced in response to the operation of said switch; a second shift register circuit including a plurality of cascade connected shift registers which are driven by a clock pulse having a second predetermined frequency lower than said first predetermined frequency for shifting the output signal from said first shift register circuit; a first logical circuit connected to receive the output signals from the shift registers of the first and last stages of said first shift register circuit for producing a pulse corresponding to the electric signal supplied to said first shift register circuit by said switch; and a second logical circuit connected to receive at least the output signals from said first and second shift register circuits and a clock pulse having a third predetermined frequency for producing clock pulses having said third predetermined frequency and whose number corresponds to the interval in which said switch is maintained open or closed when said switch is maintained open or closed for an interval longer than a predetermined interval.

Claim 3

A time correction circuit according to claim 1 which further comprises an OR gate circuit connected to receive the output signals from said first and second logical circuits.

Claim 4

A time correction circuit according to claim 1 wherein said first shift register circuit includes two shift registers each constructed to invert and shift an input signal applied thereto, said second shift register circuit includes two shift registers each constructed to shift an input applied thereto without inverting the input, said first logic circuit comprises a NOR gate circuit, and said second logic circuit comprises an AND gate circuit.

Claim 5

A time correction circuit according to claim 1 wherein said first shift register circuit includes two cascade connected shift registers each constructed to invert and shift an input signal applied thereto, said second shift register circuit includes three cascade connected shift registers each constructed to shift an input applied thereto without inverting the input, said first logic circuit comprises a first AND gate circuit including inverters at the input stage, and said second logic circuit comprises a second AND gate circuit.

Claim 6

A time correction circuit according to claim 1 wherein said first shift register circuit comprises two cascade connected shift registers each constructed to invert and shift an input signal applied thereto; said second shift register circuit comprises three cascade connected shift registers each constructed to shift an input signal without inverting the same; said first logical circuit comprises a first AND gate circuit including an inverter in the first stage; and said second logical circuit comprises a second AND gate circuit including an inverter at the first stage, a flip-flop circuit having an input terminal connected to the output terminal of said first shift register circuit and a reset terminal connected to the output terminal of said second AND gate circuit, a third AND gate circuit having an input terminal connected to the output terminal of said first shift register circuit via an inverter, and a fourth AND gate circuit connected to receive the output signal from said third AND gate circuit and a clock pulse having a frequency of 1 Hz, and wherein said time correction circuit further comprises a fifth AND gate circuit connected to receive the outputs from said first AND gate circuit and said flip-flop circuit, and an OR gate circuit connected to receive the outputs from said fourth and fifth AND gate circuits.

Claim 7

A time correction circuit according to claim 5 which further comprises a pulse generating circuit responsive to the output signal from said fifth AND gate circuit for applying a pulse corresponding to said output signal to said OR gate circuit.

Claim 8

A time correction circuit according to claim 3 which further comprises an OR gate circuit connected to receive the output signals from said NOR gate circuit and said AND gate circuit.

Claim 9

A time correction circuit according to claim 7 wherein each shift register of said first shift register circuit is driven by a clock pulse having a frequency of 32 Hz, each shift register of said second shift register circuit is driven by a clock pulse having a frequency of 1 Hz, and said AND gate circuit is connected to receive the output signals from said first and second shift register circuits and a clock pulse having a frequency of 1 to 10 Hz.

Claim 10

A time correction circuit according to claim 4 which further comprises an OR gate circuit connected to receive the output signals from said first and second AND gate circuits.

Claim 11

A time correction circuit according to claim 9 wherein each shift register of said first shift register circuit is driven by a clock pulse having a frequency of 32 Hz, each shift register of said second shift register circuit is driven by a clock pulse having a frequency of 1 Hz and said second AND gate circuit is connected to receive the output signals from said first and second shift register circuits and the clock pulse having a frequency of 1 Hz.