Gate modulated bipolar transistor

Claim 2

A gate modulated bipolar transistor including an emitter region, at least one collector region, a base region and at least one gate region integral with the base region; a first region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a first type conductivity, the first region comprising the base and gate regions; a second region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a second and opposite type conductivity, the second region comprising the emitter region; the top surface of the second region being coextensive with the bottom surface of the first region; a first P-N junction formed by the contiguous surfaces of the material of the first and second regions of opposite type conductivity; at least two spaced third regions of second type conductivity disposed in a portion of the top surface of the first region and extending into the first region a distance less than the thickness of the first region, each third region functioning as a collector region and having a top surface coextensive with the top surface of the first region a selected wall surface opposed to a selective wall surface of a mutually adjacent third region thereby defining a gate region therebetween; a second P-N junction formed by the contiguous surfaces of the material of abutting first and third regions of opposite type conductivity; the distance between the opposed selective wall surfaces of the spaced collector regions being less than 1.414 times the depletion layer width of the second P-N junction at breakdown of the device; a fourth region of first type conductivity disposed in a portion of the top surface of each of the gate regions, each fourth region having a top surface coextensive with the top surface of the third regions and the gate regions and a level of resistivity which is less than that of the gate region; the width of each fourth region is equal to less than 0.828 times the depletion layer width of the second P-N junction at breakdown; a plurality of first ohmic electrical contacts, each contact is affixed to one of the fourth regions; a second ohmic electrical contact affixed to the bottom surface of the second region; a plurality of third electrical contacts, each contact being affixed to one of the third regions, and wherein when a variable voltage source, operating between predetermined limits, is connected to the first ohmic electrical contact to drive the gate region and reverse bias is applied to the collector region via the third ohmic electrical contacts, an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 3

The transistor of claim 1 wherein the third regions are integral with each other to form one region which has an annular configuration which encompasses the gate region.

Claim 4

The transistor of claim 1 wherein a plurality of third regions are disposed in the portion of the top surface to define a plurality of gate regions, and a plurality of first contacts, each contact is disposed upon a respective gate region defined by a pair of third regions.

Claim 5

The transistor of claim 3 wherein each third region has a rectangular configuration and each gate region has a rectangular configuration.

Claim 6

The transistor of claim 2 and including a plurality of spaced concentric annular third regions disposed in the top surface portion of the first region defining a plurality of spaced annular gate regions; a plurality of first ohmic electrical contacts, each first contacts being affixed to a respective one of the gate regions, and a plurality of third ohmic electrical contacts, each third electrical contact being affixed to a respective one of the plurality of third regions.

Claim 7

The transistor of claim 1 including walls defining an annular moat in the outer peripheral portion of the transistor and extending downward from the top surface of the first region to at least intersect, and expose therein, the first P-N junction, and a layer of electrically insulating material disposed on the exposed portions of the first P-N junction in the trough.

Claim 8

An electrical circuit including two electrical terminals; a power source; a first electrical circuit means connected between the two electrical terminals and connecting the power source to the electrical load; a gate modulated bipolar transistor including an emitter region, at least one collector region, a base region and at least one gate region integral with the base region; a first region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a first type conductivity, the first region comprising the base and gate regions; a second region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a second and opposite type conductivity, the second region comprising the emitter region; the top surface of the second region being coextensive with the bottom surface of the first region; a first P-N junction formed by the contiguous surfaces of the material of the first and second regions of opposite type conductivity; at least two spaced third regions of second type conductivity disposed in a portion of the top surface of the first region and extending into the first region, a distance less than the thickness of the first region, each third region functioning as a collector region and having a top surface coextensive with the top surface of the first region a selected wall surface opposed to a selective wall surface of a mutually adjacent third region thereby defining a gate region therebetween; a second P-N junction formed by the contiguous surfaces of the material of abutting first and third regions of opposite type conductivity; the distance between the opposed selective wall surfaces of the spaced collector regions being less than 1.414 times the depletion layer width of the second P-N junction at breakdown of the device; a fourth region of first type conductivity disposed in a portion of the top surface of each of the gate regions, each fourth region having a top surface coextensive with the top surface of the third regions and the gate regions and a level of resistivity which is less than that of the gate region; the width of each fourth region is equal to less than 0.838 times the depletion layer width of the second P-N junction at breakdown; a plurality of first ohmic electrical contacts, each contact is affixed to one of the fourth regions; a second ohmic electrical contact affixed to the bottom surface of the second region; a plurality of third electrical contacts, each contact being affixed to one of the third regions, and wherein when a variable voltage source, operating between predetermined limits, is connected to the first ohmic electrical contact to drive the gate region and reverse bias is applied to the collector region via the third ohmic electrical contacts, an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of of which is modulated by the variable voltage source; a second electrical circuit means connecting the collector region to one of the electrical terminals; a third electrical circuit means connecting the emitter region to the other of the electrical terminals, and a variable voltage source, operating between predetermined limits, connected to drive the at least one gate region, wherein when a reverse bias is applied to the collector an increase in the gate-collector reverse bias decreases the emitter and collector currents and transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 9

An electrical circuit including two electrical terminals; a power source; a first electrical circuit means connected between the two electrical terminals and connecting the power source to the electrical load; a gate modulated bipolar transistor including an emitter region, at least one collector region, a base region and at least one gate region integral with the base region; a first region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a first type conductivity, the first region comprising the base and gate regions; a second region having opposed major surfaces, which are, respectively, the top and bottom surfaces thereof, and a second and opposite type conductivity, the second region comprising the emitter region; the top surface of the second region being coextensive with the bottom surface of the first region; a first P-N junction formed by the contiguous surfaces of the material of the first and second regions of opposite type conductivity; at least two spaced third regions of second type conductivity disposed in a portion of the top surface of the first region and extending into the first region, a distance less than the thickness of the first region, each third region functioning as a collector region and having a top surface coextensive with the top surface of the first region a selected wall surface opposed to a selective wall surface of a mutually adjacent third region thereby defining a gate region therebetween; a second P-N junction formed by the contiguous surfaces of the material of abutting first and third regions of opposite type conductivity; the distance between the opposed selective wall surfaces of the spaced collector regions being less than 1.414 times the depletion layer width of the second P-N junction at breakdown of the device; a fourth region of first type conductivity disposed in a portion of the top surface of each of the gate regions, each fourth region having a top surface coextensive with the top surface of the third regions and the gate regions and a level of resistivity which is less than that of the gate region; the width of each fourth region is equal to less than 0.838 times the depletion layer width of the second P-N junction at breakdown; a plurality of first ohmic electrical contacts, each contact is affixed to one of the fourth regions; a second ohmic electrical contact affixed to the bottom surface of the second region; a plurality of third electrical contacts, each contact being affixed to one of the third regions, and wherein when a variable voltage source, operating between predetermined limits, is connected to the first ohmic electrical contact to drive the gate region and reverse bias is applied to the collector region via the third ohmic electrical contacts, an increase in the gate-collector reverse bias decreases the emitter and collector currents and the transistor functions as a negative resistance element, the magnitude of of which is modulated by the variable voltage source; a second electrical circuit means connecting the collector region to one of the electrical terminals; a third electrical circuit means connecting the emitter region to the other of the electrical terminals, and a variable voltage source, operating between predetermined limits, connected to drive the at least one gate region, wherein when a reverse bias is applied to the collector an increase in the gate-collector reverse bias decreases the emitter and collector currents and transistor functions as a negative resistance element, the magnitude of which is modulated by the variable voltage source.

Claim 10

The electrical circuit of claim 7 wherein the third regions are integral with each other to form one region which has an annular configuration which encompasses the gate region.

Claim 11

The electrical circuit of claim 7 wherein a plurality of third regions are disposed in the portion of the top surface to define a plurality of gate regions, and a plurality of first contacts, each contact is disposed upon a respective gate region defined by a pair of third regions.

Claim 12

The electrical circuit of claim 9 wherein each third region has a rectangular configuration and each gate region has a rectangular configuration.

Claim 13

The electrical circuit of claim 8 and including a plurality of spaced concentric annular third regious disposed in the top surface portion of the first region defining a plurality of spaced annular gate regions; a plurality of first ohmic electrical contacts, each first contact being affixed to a respective one of the gate regions, and a plurality of third ohmic electrical contacts, each third electrical contact being affixed to a respective one of the plurality of third regions.

Claim 14

The transistor of claim 7 including walls defining an annular moat in the outer peripheral portion of the transistor and extending downward from the top surface of the first region to at least intersect, and expose therein, the first P-N junction, and a layer of electrically insulating material disposed on the exposed portion of the first P-N junction in the trough.