Patent US4032372A successfully refreshed from Google Patents.
US4032372A
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Epitaxial outdiffusion technique for integrated bipolar and field effect transistors
Assignee: International Business Machines Corp
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Filing: 1975-09-10
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Granted: 1977-06-28
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Expires: 1995-09-10
Abstract
Abstract An NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate. Subcollector-like areas of one conductivity type are diffused into selected regions of a semiconductor substrate of the opposite conductivity type. Each subcollector-like area comprises two impurities of the same conductivity type but different concentrations and diffusion rates. An epitaxial layer of the same conductivity type as the substrate is grown over the substrate. One of each pair of subcollector impurities outdiffuses completely through the epitaxial layer during the growth of the epitaxial layer and during subsequent heat treatments to define a plurality of isolated pockets of a conductivity type opposite the conductivity type of the surrounding epitaxial layer and substrate. An NPN bipolar transistor and a P channel field effect transistor subsequently are formed in respective isolated pockets. An N channel field effect transistor is formed in the epitaxial layer between the isolated pockets.
Inventors
- 👤 Madhukar B. Vora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D99/00; H10P; H10P32/00; H10P32/10; H10P32/15; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
214 words
A method for making monolithic semiconductor devices comprising the steps of: Providing a semiconductor substrate of one conductivity type, introducing two impurities of different diffusion rates and of the other conductivity type into said substrate through each of a plurality of desired surface locations, the concentration of the impurity having the lower diffusion rate being greater than the concentration of the impurity having the higher diffusion rate, forming an epitaxial layer of semiconductor material on said substrate and over said locations, said expitaxial layer being of the same conductivity type as said substrate, heating said epitaxial layer and said substrate to outdiffuse said higher diffusion rate impurity completely through said epitaxial layer to reach the surface of said epitaxial layer opposite the interface between said epitaxial layer and said substrate, forming at one of said desired surface locations a bipolar transistor wholly within the region of said epitaxial layer through which said higher diffusion rate impurity has outdiffused completely through said expitaxial layer to reach said surface of said epitaxial layer opposite said interface, said higher diffusion rate impurity forming the collector of said bipolar transistor and the other of said impurities forming the subcollector of said bipolar transistor, and forming an insulated gate field effect transistor in said epitaxial layer outside said region.
Claim 2
Independent Claim
214 words
A method for making monolithic semiconductor devices comprising the steps of: Providing a semiconductor substrate of one conductivity type, introducing two impurities of different diffusion rates and of the other conductivity type into said substrate through each of a plurality of desired surface locations, the concentration of the impurity having the lower diffusion rate being greater than the concentration of the impurity having the higher diffusion rate, forming an epitaxial layer of semiconductor material on said substrate and over said locations, said expitaxial layer being of the same conductivity type as said substrate, heating said epitaxial layer and said substrate to outdiffuse said higher diffusion rate impurity completely through said epitaxial layer to reach the surface of said epitaxial layer opposite the interface between said epitaxial layer and said substrate, forming at one of said desired surface locations a bipolar transistor wholly within the region of said epitaxial layer through which said higher diffusion rate impurity has outdiffused completely through said expitaxial layer to reach said surface of said epitaxial layer opposite said interface, said higher diffusion rate impurity forming the collector of said bipolar transistor and the other of said impurities forming the subcollector of said bipolar transistor, and forming an insulated gate field effect transistor in said epitaxial layer outside said region.
Claim 3
Dependent Claim
21 words
The method defined in claim 1 wherein said field effect transistor is formed in said epitaxial layer between said desired locations.
Claim 4
Dependent Claim
14 words
The method defined in claim 1 wherein said introducing step is a diffusion step.
Claim 5
Dependent Claim
13 words
The method defined in claim 3 wherein said impurities are arsenic and phosphorus.
Claim 6
Independent Claim
223 words
A method of making monolithic semiconductor devices comprising the steps of: providing a semiconductor substrate of one conductivity type, introducing two impurities of different diffusion rates and of the other conductivity type into said substrate through each of a plurality of desired surface locations, the concentration of the impurity of having the lower diffusion rate being greater than the concentration of the impurity having the higher diffusion rate, forming an epitaxial layer of semiconductor material on said substrate and over said locations, said epitaxial layer being of the same conductivity type as said substrate, heating said epitaxial layer and said substrate to outdiffuse said higher diffusion rate impurity completely through said epitaxial layer to reach the surface of said epitaxial layer opposite the interface between said epitaxial layer and said substrate, forming at respective ones of said desired locations a bipolar transistor and an insulated gate field effect transistor wholly within the region of said epitaxial layer through which said higher diffusion rate impurity has outdiffused completely through said epitaxial layer to reach said surface of said epitaxial layer opposite said interface, said higher diffusion rate impurity forming the collector of said bipolar transistor and the other of said impurities forming the subcollector of said bipolar transistor, and forming another insulated gate field effect transistor in said epitaxial layer between said desired locations.
Claim 7
Independent Claim
223 words
A method of making monolithic semiconductor devices comprising the steps of: providing a semiconductor substrate of one conductivity type, introducing two impurities of different diffusion rates and of the other conductivity type into said substrate through each of a plurality of desired surface locations, the concentration of the impurity of having the lower diffusion rate being greater than the concentration of the impurity having the higher diffusion rate, forming an epitaxial layer of semiconductor material on said substrate and over said locations, said epitaxial layer being of the same conductivity type as said substrate, heating said epitaxial layer and said substrate to outdiffuse said higher diffusion rate impurity completely through said epitaxial layer to reach the surface of said epitaxial layer opposite the interface between said epitaxial layer and said substrate, forming at respective ones of said desired locations a bipolar transistor and an insulated gate field effect transistor wholly within the region of said epitaxial layer through which said higher diffusion rate impurity has outdiffused completely through said epitaxial layer to reach said surface of said epitaxial layer opposite said interface, said higher diffusion rate impurity forming the collector of said bipolar transistor and the other of said impurities forming the subcollector of said bipolar transistor, and forming another insulated gate field effect transistor in said epitaxial layer between said desired locations.
Claim 8
Dependent Claim
62 words
The method defined in claim 5 wherein said bipolar transistor and said field effect transistors are formed by diffusion, the base of said bipolar transistor and the source and drain of one of said field effect transistors being diffused simultaneously, and the emitter of said bipolar transistor and the source and drain of another of said field effect transistors being diffused simultaneously.
Claim 9
Dependent Claim
16 words
The method defined in claim 6 wherein arsenic is used for the diffusion of said emitter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-27 | 1980-12-27 | 1981-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-27 | 1984-12-27 | 1985-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-27 | 1988-12-27 | 1989-06-28 | $7700.00 | Window Closed / Lapsed |