Deep diode silicon controlled rectifier

Claim 2

A process for making a semiconductor device comprising (a) selecting a body of semiconductor material having a predetermined level of resistivity, a predetermined type conductivity and two major opposed surfaces which are, respectively, the top and bottom surfaces thereof, at least one of the major surfaces having a preferred planar crystal orientation which is one selected from the group consisting of (100), (110), and (111), and a vertical axis of the body being substantially aligned parallel with a first axis of the crystal structure which is substantially perpendicular to at least the major surface having the preferred planar orientation; (b) vapor depositing a first array of metal wires having a selected configuration on the major surface of the body having a preferred crystal planar orientation, the metal comprising at least one material suitable for imparting to a portion of the body a predetermined type conductivity and a predetermined level of resistivity, each wire being oriented substantially parallel with a preferred second crystal axis of the material of the body; (c) heating the body and the array of metal wires to a predetermined elevated temperature sufficient to form an array of liquid wires of metal-rich semiconductor material on the surface of the body; (d) establishing a temperature gradient in the body substantially perpendicular to the two opposed major surfaces, the major surface having the array of liquid wires being at the lower temperature; (e) migrating the first array of metal wires by thermal gradient zone melting entirely through the body from the major surface of lower temperature to the major surface of higher temperature substantially parallel with the first crystal axis to form a lamellar body of semiconductor material of at least one group of two integral pairs of first and second regions of alternate and opposite type conductivity and to form a P-N junction between each mutual pair of regions of opposite type conductivity, the first region of one pair and the second region of the second pair each having a surface area comprising, respectively, one of the two major opposed surfaces of the body, the first and third regions of each group having a first type conductivity and the second and fourth regions of each group having a second, and opposite, type conductivity; (f) affixing a first electrical contact to a surface area of the first region of the group; (g) affixing a second electrical contact to a surface area of the fourth region of the group, and (h) affixing a third electrical contact to a surface area of one of the second and third regions of the group.

Claim 3

The process of claim 1 including practicing the process step prior to the vapor depositing of the first array of metal wires of selectively etching the surface of the body of semiconductor material to form an array of trough-like depression into which the metal wires are vapor deposited.

Claim 4

The process of claim 2 wherein the material of the body is one selected from the group consisting of silicon, silicon carbide, gallium arsenide and germanium.

Claim 5

The process of claim 3 wherein the material of the body is silicon of N-type conductivity and the material of the first array of metal wires is aluminum.

Claim 6

The process of claim 1 including the process step practiced after migrating the first array of metal wires and before affixing the first electrical contact of vapor depositing a second array of metal wires on the surface of at least each fourth region of each group, and the body of semiconductor material on which the first array is deposited, and overlapping at least a predetermined portion of the third region of each group, and migrating the second array of metal wires through the body to alter the level of dopant impurity concentration in the semiconductor material of at least the fourth region in each group.

Claim 7

The process of claim 5 including practicing the process step prior to the vapor depositing of the second array of metal wires of selectively etching the surface of the body of semiconductor material to form an array of troughlike depression into which the metal wires are vapor deposited.

Claim 8

The process of claim 6 wherein the material of the body is one selected from the group consisting of silicon, silicon carbide, gallium arsenide and germanium.

Claim 9

The process of claim 7 wherein the material of the body is silicon of N-type conductivity and the material of the first array of metal wires is aluminum, the material of the second array of metal wires is one of the metal alloys selected from the group consisting of gold and antimony, and tin and antimony.

Claim 10

The process of claim 1 wherein the preferred crystal planar orientation is (111) and the first preferred crystal axis is <111>.

Claim 11

The process of claim 9 wherein the second preferred crystal axis is one selected from the group consisting of <011>, <101>, <110>, <112>, <211> and <121>.

Claim 12

The process of claim 10 wherein the width of each liquid wire is less than 500 microns.

Claim 13

The process of claim 1 wherein the preferred crystal planar orientation is (110), the first preferred crystal axis is <110>, and the second preferred crystal axis is <110>.

Claim 14

The process of claim 12 wherein the width of each liquid wire is less than 150 microns.

Claim 15

The process of claim 1 wherein the preferred crystal planar orientation is (100), the first preferred crystal axis <100>, and the second preferred crystal axis is one selected from the group consisting of <011> and <011>.

Claim 16

The process of claim 1 wherein the preferred crystal planar orientation is one selected from the group consisting of (100) and (111), the first array of metal wires define a plurality of concentric rectangular configurations, the wires defining two parallel sides of each rectangle being oriented substantially parallel to a preferred third crystal axis of the material of the body which is perpendicular to the second crystal axis of orientation of the other two parallel sides of the rectangle, and migration of each array of metal wires through the body produces at least a four region device including three concentric and abutting rectangular regions disposed about a centrally disposed region.

Claim 17

The process of claim 15 including practicing the process step prior to the vapor depositing of the first array of metal wires of selectively etching the surface of the body of semiconductor material to form an array of trough-like depressions into which the metal wires are vapor deposited.

Claim 18

A process for making a semiconductor device comprising (a) selecting a body of semiconductor material having a predetermined level of resistivity, a predetermined first type conductivity and two major opposed surfaces which are, respectively, the top and bottom surfaces thereof, at least one of the major surfaces having a preferred planar crystal orientation which is one selected from the group consisting of (100), (110), and (111), and a vertical axis of the body being substantially aligned parallel with a first axis of the crystal structure which is substantially perpendicular to at least the major surface having the preferred planar orientation; (b) vapor depositing a first array of metal wires having a selected configuration on the major surface of the body having a preferred crystal planar orientation, the metal comprising at least one material suitable for imparting to a portion of the material of the body a predetermined type conductivity and a predetermined level of resistivity, each wire being oriented substantially parallel with a preferred second crystal axis of the material of the body; (c) heating the body and the array of metal wires to a predetermined elevated temperature sufficient to form an array of liquid wires of metal-rich semiconductor material on the surface of the body; (d) establishing a temperature gradient in the body substantially perpendicular to the two opposed major surfaces, the major surface having the array of liquid wires being at the lower temperature, (e) migrating the first array of metal wires by thermal gradient zone melting entirely through the body from the major surface of lower temperature to the major surface of higher temperature substantially parallel with the first crystal axis to form a lamellar body of semiconductor material of at least one group of three regions of alternate and opposite type conductivity and to form a P-N junction between each pair of regions of opposite type conductivity, the first and third regions of each group having the same first type conductivity and the second region of each group having a second and opposite type conductivity; (f) forming a plurality of fourth regions of second conductivity type in the third region of only one group and a plurality of P-N junctions at the abutting surfaces of the material of each of the fourth regions and the third region of opposite type conductivity, each of the fourth regions having a surface area coextensive with a surface of the third region; affixing a first electrical contact to a surface area of the first region; (g) affixing a second electrical contact to both the surface areas of the fourth regions and a selected portion of the coextensive surface of the third region, and (h) affixing a third electrical contact to another selected portion of the third region.

Claim 19

A process for making a semiconductor device comprising (a) selecting a body of semiconductor material having a predetermined level of resistivity, a predetermined first type conductivity and two major opposed surfaces which are, respectively, the top and bottom surfaces thereof, at least one of the major surfaces having a preferred planar crystal orientation which is one selected from the group consisting of (100), (110), and (111), and a vertical axis of the body being substantially aligned parallel with a first axis of the crystal structure which is substantially perpendicular to at least the major surface having the preferred planar orientation; (b) vapor depositing a first array of metal wires having a selected configuration on the major surface of the body having a preferred crystal planar orientation, the metal comprising at least one material suitable for imparting to a portion of the material of the body a predetermined type conductivity and a predetermined level of resistivity, each wire being oriented substantially parallel with a preferred second crystal axis of the material of the body; (c) heating the body and the array of metal wires to a predetermined elevated temperature sufficient to form an array of liquid wires of metal-rich semiconductor material on the surface of the body; (d) establishing a temperature gradient in the body substantially perpendicular to the two opposed major surfaces, the major surface having the array of liquid wires being at the lower temperature, (e) migrating the first array of metal wires by thermal gradient zone melting entirely through the body from the major surface of lower temperature to the major surface of higher temperature substantially parallel with the first crystal axis to form a lamellar body of semiconductor material of at least one group of three regions of alternate and opposite type conductivity and to form a P-N junction between each pair of regions of opposite type conductivity, the first and third regions of each group having the same first type conductivity and the second region of each group having a second and opposite type conductivity; (f) forming a plurality of fourth regions of second conductivity type in the third region of only one group and a plurality of P-N junctions at the abutting surfaces of the material of each of the fourth regions and the third region of opposite type conductivity, each of the fourth regions having a surface area coextensive with a surface of the third region; affixing a first electrical contact to a surface area of the first region; (g) affixing a second electrical contact to both the surface areas of the fourth regions and a selected portion of the coextensive surface of the third region, and (h) affixing a third electrical contact to another selected portion of the third region.

Claim 20

The process of claim 17 including practicing the process step prior to the vapor depositing of the first array of metal wires of selectively etching the surface of the body of semiconductor material to form an array of trough-like depressions into which the metal wires are vapor deposited.

Claim 21

The process of claim 18 wherein the material of the body is one selected from the group consisting of silicon, silicon carbide, gallium arsenide and germanium.

Claim 22

The process of claim 19 wherein the material of the body is silicon of N-type conductivity and the material of the first array of metal wires is aluminum.

Claim 23

The process of claim 20 wherein the forming of the plurality of fourth regions is practiced by a diffusion process.

Claim 24

The process of claim 20 wherein the forming of the fourth regions is practiced by an alloying process.

Claim 25

The process of claim 20 wherein the forming of the fourth regions is practiced by a thermal gradient zone melting process of: vapor depositing a second array of metal on the selected portion of the surface of the third region; and migrating the second array of metal into the third region to a depth less than the thickness of the third region to form the plurality of fourth regions and the P-N junctions at the abutting surfaces of the material of each of the fourth regions and the third regions of opposite type conductivity.

Claim 26

The process of claim 17 wherein the thermal migrating of the first array of metal wires produces at least two groups of three regions of alternate and opposite type conductivity, one group having a first region having a surface area comprising the bottom surface of the body and one of the other group having a third region having a surface area comprising the top surface of the body; and including the additional process steps; vapor depositing a second array of metal wires having a selected configuration on the surface of the body having the preferred planar orientation, migrating the second array of metal wires through the body by thermal gradient zone melting to form a fifth region of first type conductivity of a selected dopant impurity concentration disposed between and in abutment with the third region of one group and the first region of the next adjacent group, to form a fourth P-N junction by the abutting surfaces of the material of the third region of the one group and the fifth region and to form a fifth P-N junction by the abutting surfaces of the material of the fifth region and the first region of the next adjacent group.

Claim 27

The process of claim 24 wherein the material of each fifth region is recrystallized semiconductor material of the body and has a substantially uniform level of dopant impurity concentration throughout the region.

Claim 28

The process of claim 25 including practicing the process step prior to the vapor depositing of the first and second arrays of metal wires of selectively etching the surface of the body of semiconductor material to form an array of troughlike depressions into which the metal wires are vapor deposited.

Claim 29

The process of claim 26 wherein the material of the body is one selected from the group consisting of silicon, silicon carbide, gallium arsenide and germanium.

Claim 30

The process of claim 27 wherein the material of the body is silicon of N-type conductivity and the material of the first array of metal wires is aluminum.

Claim 31

The process of claim 28 wherein the forming of the plurality of fourth regions is practiced by a diffusion process.

Claim 32

The process of claim 28 wherein the forming of the fourth regions is practiced by an alloying process.

Claim 33

The process of claim 28 wherein the forming of the fourth regions is practiced by a thermal gradient zone melting process of vapor depositing a third array of metal on the selected portion of the surface area of the third region of the one group; and migrating the third array of metal into the third region of the one group to a depth less than the thickness of the third region to form the plurality of fourth regions and the P-N junction at the abutting surfaces of each of the fourth regions and the third regions of opposite type conductivity.

Claim 34

The process of claim 17 wherein the preferred crystal planar orientation is (111) and the first preferred crystal axis is <111>.

Claim 35

The process of claim 32 wherein the second preferred crystal axis is one selected from the group consisting of <011>, <101>, <110>, <112>, <211> and <121>.

Claim 36

The process of claim 33 wherein the width of each liquid wire is less than 500 microns.

Claim 37

The process of claim 17 wherein the preferred crystal planar orientation is (110), the first preferred crystal axis is <110>, and the second preferred crystal axis is <110>.

Claim 38

The process of claim 35 wherein the width of each liquid wire is less than 150 microns.

Claim 39

The process of claim 17 wherein the preferred crystal planar orientation is (100), the first preferred crystal axis <100>, and the second preferred crystal axis is one selected from the group consisting of <011> and <011>.