Patent US4031416A successfully refreshed from Google Patents.
US4031416A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor amplification means combining two cascaded transistor amplifiers of high inverse impedances
Assignee: RCA Licensing Corp
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Filing: 1976-03-08
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Granted: 1977-06-21
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Expires: 1996-03-08
Abstract
Abstract The present invention relates to semiconductor amplification means, which may be fabricated as a monolithic semiconductor structure, for use in an automatic gray scale control circuit for a color television receiver. During the blanking interval, the control circuit senses the cut-off voltage of each gun of a three gun color cathode ray tube and stores that voltage. During the video field, the stored voltage is used to energize the driver for the individual gun and to bias that gun. The AGS control function for each gun requires two amplifiers of high current gain, high inverse impedance, only one of which is on at a time, and a consolidation of the sensing and output functions in two terminals. These functions are achieved in a four transistor configuration in which two cascaded pairs of emitter follower transistor amplifiers are connected in a closed loop. A high inverse impedance is achieved by the provision of a second emitter in the output transistor of each cascaded pair, coupled to the base of the preceding transistor to insure turn off.
Inventors
- 👤 William Peil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:24
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/73
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
Semiconductor amplification means comprising: a. four transistors of like conductivity type wherein 1. the emitter of the first transistor (Q1) is coupled to the base of the second transistor (Q2), 2. the transistor Q2 has a first and a second emitter, said first emitter of Q2 being coupled to the base of the third transistor (Q3), and the second emitter of Q2 being coupled to the base of Q1 to insure turn off of Q2 when Q1 is turned off, 3. the emitter of Q3 is coupled to the base of the fourth transistor (Q4), 4. the transistor Q4 has a first and a second emitter, said first emitter of Q4 being coupled to the base of Q1, and said second emitter of Q3 being coupled to the base of Q3 to insure turn off of Q4 when Q3 is turned off, and b. a first terminal for connection to a d.c. source coupled to the collectors of Q1, Q2, Q3, Q4.
Claim 2
Dependent Claim
162 words
Semiconductor amplification means comprising: a. four transistors of like conductivity type wherein 1. the emitter of the first transistor (Q1) is coupled to the base of the second transistor (Q2), 2. the transistor Q2 has a first and a second emitter, said first emitter of Q2 being coupled to the base of the third transistor (Q3), and the second emitter of Q2 being coupled to the base of Q1 to insure turn off of Q2 when Q1 is turned off, 3. the emitter of Q3 is coupled to the base of the fourth transistor (Q4), 4. the transistor Q4 has a first and a second emitter, said first emitter of Q4 being coupled to the base of Q1, and said second emitter of Q3 being coupled to the base of Q3 to insure turn off of Q4 when Q3 is turned off, and b. a first terminal for connection to a d.c. source coupled to the collectors of Q1, Q2, Q3, Q4.
Claim 3
Dependent Claim
99 words
Semiconductor amplification means as set forth in claim 1, having in addition thereto a pair of control terminals coupled respectively to the base of Q1 and to the base of Q3 for causing Q1, Q2 to conduct current from said source to one control terminal and Q3, Q4 to be nonconductive at a low leakage current in response to control signals of one polarity; and for causing Q1, Q2 to be nonconductive at a low leakage current and Q3, Q4 to conduct current from said source to the other control terminal in response to control signals of opposite polarity.
Claim 4
Dependent Claim
90 words
Semiconductor amplification means as set forth in claim 1 fabricated in monolithic structure comprising: a. a semiconductor substrate having a first region of a first conductivity type forming a common collector region for all four transistors, b. four separate diffusions of a complementary conductivity type in said first region forming bases, and c. six separate diffusions of said first conductivity type in said base diffusions forming emitters, one emitter diffusion in the base regions of Q1 and Q3 and two emitter diffusions in the base regions of Q2 and Q4.
Claim 5
Dependent Claim
22 words
Monolithic semiconductor amplification means as set forth in claim 3 wherein said first region is an epitaxial layer on said semiconductor substrate,
Claim 6
Dependent Claim
22 words
A monolithic semiconductor amplification means as set forth in claim 4 wherein a four part metallization is provided for said emitter-base interconnections.
Claim 7
Dependent Claim
63 words
Monolithic semiconductor amplification means as set forth in claim 5 wherein a. a first terminal means is applied to the metallization interconnecting the base of Q1, the second emitter of Q2 and the first emitter of Q4, b. a second terminal means is applied to the metallization interconnecting the first emiter of Q2, the base of Q3 and the second emitter of Q4.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |