Digital double differential phase-locked loop

Claim 2

A digital double differential phase-locked loop for extraction of a bit clock from digital data comprising: a source of digital data; first means to provide a reference pulse train having a predetermined reference frequency; second means including a voltage controlled oscillator to provide said bit clock having a repetition frequency locked to said repetition frequency of the bits of said digital data; third means coupled to said first means to divide said reference frequency by a selected one of a first division factor and a second division factor different than said first division factor; fourth means coupled to said second means to divide said repetition frequency by a selected one of a third division factor and a fourth division factor different than said first, second and third division factors; fifth means coupled to said third and fourth means to compare the phase of the output signals of said third and fourth means and to produce a first control signal proportional to the phase difference between the output signals of said third and fourth means; sixth means coupled to said fifth means and said second means to couple said first control signal to said voltage controlled oscillator to adjust the phase of said bit clock to lock said bit clock to the bits of said digital data; and seventh means coupled to said source, said second means and said third and fourth means to produce a phase slip rate signal to select the appropriate one of said first and second division factors for said third mans and to select the appropriate one of said third and fourth division factors for said fourth means.

Claim 3

A phase-locked loop according to claim 1, wherein said first division factor is J, said second division factor is K, said third division factor is L, and said fourth division factor is M, where J, K, L and M are integers greater than one and satisfy the equation JM-KL =1.

Claim 4

A phase-locked loop according to claim 2, wherein said third means includes a first digital counter having a division factor selected from the values J and K, and said fourth means includes a second digital counter having a division factor selected from the values of L and M.

Claim 5

A phase-locked loop according to claim 3, wherein said first counter has a division factor of J and said second counter has a division factor of L during the absence of said phase slip rate signal, and said first counter has a division factor of K and said second counter has a division factor of M during the presence of said phase slip rate signal.

Claim 6

A phase-locked loop according to claim 4, wherein said fifth means includes a first digital phase comparator.

Claim 7

A phase-locked loop according to claim 5, wherein said sixth means includes a low pass filter.

Claim 8

A phase-locked loop according to claim 6, wherein said seventh means includes a second digital phase comparator coupled to said second means and said source responsive to said data and said bit clock to produce a second control signal proportional to the phase difference between said bit clock and said data, a digital filter coupled to said first means and said second phase comparator responsive to said second control signal to provide a frequency value proportional to said second control signal, and a digitally controlled rate generator coupled to said first means and said digital loop filter responsive to said frequency value to produce said phase slip rate signal.

Claim 9

A phase-locked loop according to claim 7, further including eighth means coupled to said source and said digital loop filter to cause said digital loop filter to hold said frequency value provide by the last detected bit of said data when loss of said data for a predetermined length of time is detected.

Claim 10

A phase-locked loop according to claim 7, wherein said second phase comparator includes a D-type filp flop having its D input coupled to said second means responsive to said bit clock, its clock input coupled to said source responsible to the bits of said data and its Q output to provide said second control signal.

Claim 11

A phase-locked loop according to claim 7, wherein said second phase comparator includes a first D-type flip flop having its D input coupled to said second means responsive to said bit clock, its clock input coupled to said source responsive to the bits of said data and its Q output to provide one bit of two bits of said second control signal, a delay circuit having a 1/4-bit delay coupled to said second means to delay said bit clock 1/4 of a bit, and a second D-type flip flop having its D input coupled to the output of said delay circuit responsive to said delayed bit clock, its clock input coupled to said source responsive to the bits of said data and its Q output to provide the other bit of said two bits of said second control signal.

Claim 12

A phase-locked loop according to claim 7, wherein said second phase comparator includes a delay circuit having a 1/4-bit delay coupled to said second means to delay said bit clock 1/4-bit, a four stage register having a clock input coupled to said source responsive to the bits of said data, a first input coupled to said second means responsive to said bit clock, a second input coupled to said delay circuit responsive to said delayed bit clock, a first output providing a plus/minus phase error signal of a present sample of said data, a second output providing a large/small phase error signal of said present sample of said data, a third output providing a plus/minus phase error signal of a previous state of said data and a fourth output providing a large/small phase error signal of said previous state of said data, and a 16×2 read only memory having two outputs coupled to said first, second, third and fourth outputs of said register, said memory being wired according to a given set of rules to provide on one output thereof a plus/minus phase error signal for a next state of said data and on the other output thereof a large/small phase error signal for said next state of said data, said one output being coupled to a third input of said register to provide said signal on said third output and said other output being coupled to a fourth input of said register to provide said signal on said fourth output, said delay circuit, said register and said memory cooperating to provide negative frequency errors for clockwise changes of phase states of said data and positive frequency errors for counter-clockwise changes of phase states of said data in accordance with said set of rules.

Claim 13

A phase-locked loop according to claim 1, wherein said second phase comparator further includes a D-type flip flop having its D input coupled to said one output of said memory and its clock input coupled to said third means responsive to transitions from most significant bits to least significant bits to produce said second control signal.

Claim 14

A phase-locked loop according to claim 7, wherein said digital loop filter includes a first serial adder/subtractor circuit having one input coupled to said second phase comparator responsive to said second control signal and a first correction factor, said second control signal and said first correction factor representing a frequency correction, a first shift register coupled to the output of said first circuit and said first means to provide a frequency signal for coupling to the other input of said first circuit, and a second serial adder/subtractor circuit having one input coupled to the output of said first shift register and its other input coupled to said second phase comparator responsive to said second control signal and a second correction factor, said second control signal and said second correction factor representing a phase correction.

Claim 15

A phase-locked loop according to claim 13, wherein said rate generator includes a serial adder circuit having one input coupled to the output of said second circuit, and a second shift register coupled to said first means, the output of said serial adder circuit and the other input of said serial adder circuit, said serial adder circuit producing said phase slip rate signal.

Claim 16

A phase-locked loop according to claim 13, further including a data detector coupled to said source to detect the presence and absence of said data, and logic circuitry coupled to said data detector and between said second phase comparator and each of said first and second circuits to hold said frequency value provided by the last detected bit of said data during absence of said data for a predetermined length of time.

Claim 17

A phase-locked loop according to claim 7, wherein said rate generator includes a serial adder circuit having one input coupled to the output of said digital loop filter, and a shift register coupled to said first means, the output of said serial adder circuit and the other input of serial adder circuit, said serial adder circuit producing said phase slip rate signal.

Claim 18

A phase-locked loop according to claim 1, wherein said fifth means includes a digital phase comparator.

Claim 19

A phase-locked loop according to claim 1, wherein said sixth means includes a low pass filter.

Claim 20

A phase-locked loop according to claim 1, wherein said seventh means includes a digital phase comparator coupled to said second means and said source responsive to said data and said bit clock to produce a second control signal proportional to the phase difference between said bit clock and said data, a digital loop filter coupled to said first means and said phase comparator responsive to said second control signal to provide a frequency value proportional to said second control signal, and a digitally controlled rate generator coupled to said first means and said digital loop filter responsive to said frequency value to produce said phase slip rate signal.

Claim 21

A phase-locked loop according to claim 19, wherein eighth means coupled to said source and said digital loop filter to cause said digital loop filter to hold said frequency value provided by the last detected bit of said data when loss of said data for a predetermined length of time is detected.

Claim 22

A phase-locked loop according to claim 19, wherein said phase comparator includes a D-type flip flop having its D input coupled to said second means responsive to said bit clock, its clock input coupled to said source responsive to the bits of said data and its Q output to provide said second control signal.

Claim 23

A phase-locked loop according to claim 19, wherein said phase comparator includes a first D-type flip flop having its D input coupled to said second means responsive to said bit clock, its clock input coupled to said source responsive to the bits of said data and its Q output to provide one bit of two bits of said second control signal, a delay circuit having a 1/4-bit delay coupled to said second means to delay said bit clock 1/4 of a bit, and a second D-type flip flop having its D input coupled to the output of said delay circuit responsive to said delayed bit clock, its clock input coupled to said source responsive to the bits of said data and its Q output to provide the other bit of said two bits of said second control signal.

Claim 24

A phase-locked loop according to claim 19, wherein said phase comparator includes a delay circuit having a 1/4-bit delay coupled to said second means to delay said bit clock 1/4-bit, a four stage register having a clock input coupled to said source responsive to the bits of said data, a first input coupled to said second means responsive to said bit clock, a second input coupled to said delay circuit responsive to said delayed bit clock, a first output providing a plus/minus phase error signal of a present sample of said data, a second output providing a large/small phase error signal of said present sample of said data, a third output providing a plus/minus phase error signal of a previous state of said data annd a fourth output providing a large/small phase error signal of said previous state of said data, and a 16×2 read only memory having two outputs coupled to said first, second, third and fourth outputs of said register, said memory being wired according to a given set of rules to provide on one output thereof a plus/minus phase error signal for a next state of said data and on the other output thereof a large/small phase error signal for said next state of said data, said one output being coupled to a third input of said register to provide said signal on said third output and said other output being coupled to a fourth input of said register to provide said signal on said fourth output, said delay circuit, said register and said memory cooperating to provide negative frequency errors for clockwise changes of phase states of said data and positive frequency errors for counter-clockwise changes of phase states of said data in accordance with said set of rules.

Claim 25

A phase-locked loop according to claim 23, wherein said phase comparator further includes a D-type flip flop having its D input coupled to said one output of said memory and its clock input coupled to said third means responsive to transitions from most significant bits to least significant bits to produce said second control signal.

Claim 26

A phase-locked loop according to claim 19, wherein said digital loop filter includes a first serial adder/subtractor circuit having one input coupled to said phase comparator responsive to said second control signal and a first correction factor, said second control signal and said first correction factor representing a frequency correction, a first shift register coupled to the output of said first circuit and said first means to provide a frequency signal for coupling to the other input of said first circuit, and a second serial adder/subtractor circuit having one input coupled to the output of said first shift register and its other input coupled to said phase comparator responsive to said second control signal and a second correction factor, said second control signal and said second correction factor representing a phase correction.

Claim 27

A phase-locked loop according to claim 25, wherein said rate generator includes a serial adder circuit having one input coupled to the output of said second circuit, and a second shift register coupled to said first means, the output of said serial adder circuit and the other input of said serial adder circuit, said serial adder circuit producing said phase slip rate signal.

Claim 28

A phase-locked loop according to claim 25, further including a data detector coupled to said source to detect the presence and absence of said data, and logic circuitry coupled to said data detector and between said phase comparator and each of said first and second circuits to hold said frequency value provided by the last detected bit of said data during absence of said data for a predetermined length of time.

Claim 29

A phase-locked loop according to claim 19, wherein said rate generator includes a serial adder circuit having one input coupled to the output of said digital loop filter, and a shift register coupled to said first means, the output of said serial adder circuit and the other input of serial adder circuit, said serial adder circuit producing said phase slip rate signal.

Claim 30

A phase-locked loop according to claim 1, wherein said seventh means includes a delay circuit having a 1/4-bit delay coupled to said second means to delay said bit clock 1/4-bit, a four stage register having a clock input coupled to said source responsive to the bits of said data, a first input coupled to said second means responsive to said bit clock, a second input coupled to said delay circuit responsive to said delayed bit clock, a first output providing a plus/minus phase error signal of a present sample of said data, a second output providing a large/small phase error signal of said present sample of said data, a third output providing a plus/minus phase error signal of a previous state of said data and a fourth output providing a large/small phase error signal of said previous state of said data, a 16 × 2 read only memory having two outputs coupled to said first, second, third and fourth outputs of said register, said memory being wired according to a given set of rules to provide on one output thereof a plus/minus phase error signal for a next state of said data and on the other output thereof a large/small phase error signal for said next state of said data, said one output being coupled to a third input of said register to provide said signal on said third output and said other output being coupled to a fourth input of said register to provide said signal on said fourth output, said delay circuit, said register and said memory cooperating to provide negative frequency errors for clockwise changes of phase states of said data and positive frequency errors for counter-clockwise changes of phase states of said data in accordance with said set of rules, a D-type flip flop having its D input coupled to said one output of said memory and its clock input coupled to said third means responsive to transitions from most significant bits to least significant bits to produce said second control signal a first serial adder/subtractor circuit having one input coupled to the Q output of said flip flop responsive to said second control signal and a first correction factor, said second control signal and said first correction factor representing a frequency correction, a first shift register coupled to the output of said first circuit and said first means to provide a frequency signal for coupling to the other input of said first circuit, a second serial adder/subtractor circuit having one input coupled to the output of said first shift register and the other input coupled to the Q output of said flip flop responsive to said second control signal and a second correction factor, said second control signal and said second factor representing a phase correction, a serial adder circuit having one input coupled to the output of said second circuit, and a second shift register coupled to said first means, the output of said serial adder circuit and the other input of said serial adder circuit, said serial adder circuit producing said phase slip rate signal.

Claim 31

A phase-locked loop according to claim 29, further including a third correction factor, a multiplexer coupled to said first correction factor, said third correction factor, said other output of said memory and said first circuit, said signal on said other output of said memory controlling said multiplexer to couple one or the other of said first and third correction factor to said first circuit.