Fetch instruction for operand address calculation

Claim 2

In a computer system having storage for storing executable and non-directly executable instructions and operands, said directly executable instructions including for every non-directly executable instruction a predetermined directly executable instruction having bit fields for performing instruction fetch phase and operand address calculation for an associated non-directly executable instruction, and a central processing unit for fetching and executing instructions from storage, the improvement comprising: identifying means within said central processing unit for identifying non-directly executable instructions fetched from storage, means responsive to said identifying means indentifying a non-directly executable instruction for retrieving from storage an associated predetermined directly executable instruction having bit fields for performing instruction fetch phase and operand address calculation of said identified non-directly executable instruction, and means responsive to bits in said bit fields of said fetched predetermined directly executable instruction to re-fetch said identified non-directly executable instruction, to compute operand addresses for operands in said non-directly executable instruction as specified in said predetermined directly executable instruction and to store said computed operand addresses to facilitate retrieval of said operands.

Claim 3

The computer system of claim 1 wherein said means responsive to said bits in said bit fields of said associated predetermined directly executable instruction is the same means in said central processing unit for computing operand addresses and storing computed operand addresses for other directly executable instructions.

Claim 4

The computer system of claim 1 wherein said bit fields in said associated predetermined directly executable instruction for re-fetching said identified non-directly executable instructon include a base bit field for addressing a register containing storage address bits and a displacement bit field to be combined with said storage address bits and thereby form a storage address for re-fetching said identified non-directly executable instruction.

Claim 5

The computer system of claim 1 wherein said bit fields in said associated predetermined directly executable instruction for computing said operand addresses include a first bit field having bits for addressing a register for storing first computed operand address bits for addressing storage to fetch a first operand to be used during simulated execution of said identified non-directly executable instruction and a second bit field having bits for addressing a register for storing last computed operand address bits for a last operand to be used during simulated execution of said identified non-directly executable instruction.

Claim 6

The computer system of claim 4 further comprising selective operable means for incrementing said first bit field bits to form incremented register address bits for addressing another register for storing another operand address bits for addressing said storage to fetch another operand to be used during said simulated execution of said identified non-directly executable instruction if said second bit field address bits are greater than said incremented register address bits.

Claim 7

In a computer system having an addressable storage for storing directly executable and non-directly executable instructions and operands and directly executable instructions including for every non-directly executable instruction a predetermined directly executable instruction having bit fields for performing instruction fetch phase and operand address calculation for an associated non-directly executable instruction, and a central processing unit, said central processing unit including first register means for storing directly executable and non-directly executable instructions fetched from said addressable storage, means for decoding said directly executable and non-directly executable instructions to determine the type of instruction and the operation to be performed, second register means for receiving portions of said instruction stored in said first register means, a stack of addressable registers, stack register addressing means and arithmetic and logic means, the improvement comprising means within said decoding means for identifying non-directly executable instructions fetched from storage, means reponsive to identification of a non-directly executable instruction for retrieving from said storage an associated predetermined directly executable instruction having first bit fields for defining the storage location of said identified non-directly executable instruction and second bit fields for defining stack register addresses for selecting stack registers to store calculated operand addresses of operands to be used during simulated execution of said identified non-directly executable instruction, means responsive to bits in said first bit fields in said associated predetermined directly executable instruction to form an address for re-fetching said identified non-directly executable instruction from storage, means for examining bits in said second bit fields in said associated predetermined directly executable instruction to form addresses for addressing said stack of addressable registers under conditions defined by the bits in said second bit fields, and means for transferring said formed addresses to said stack register addressing means whereby stack registers are selected for storing addresses of operands computed from address date in said re-fetched non-directly executable instruction during simulated execution thereof.

Claim 8

In a computer system having an addressable storage for storing directly executable and non-directly executable instructions and operands and directly executable instructions including for every non-directly executable instruction a predetermined directly executable instruction having bit fields for performing instruction fetch phase and operand address calculation for an associated non-directly executable instruction, and a central processing unit, said central processing unit including first register means for storing directly executable and non-directly executable instructions fetched from said addressable storage, means for decoding said directly executable and non-directly executable instructions to determine the type of instruction and the operation to be performed, second register means for receiving portions of said instruction stored in said first register means, a stack of addressable registers, stack register addressing means and arithmetic and logic means, the improvement comprising means within said decoding means for identifying non-directly executable instructions fetched from storage, means reponsive to identification of a non-directly executable instruction for retrieving from said storage an associated predetermined directly executable instruction having first bit fields for defining the storage location of said identified non-directly executable instruction and second bit fields for defining stack register addresses for selecting stack registers to store calculated operand addresses of operands to be used during simulated execution of said identified non-directly executable instruction, means responsive to bits in said first bit fields in said associated predetermined directly executable instruction to form an address for re-fetching said identified non-directly executable instruction from storage, means for examining bits in said second bit fields in said associated predetermined directly executable instruction to form addresses for addressing said stack of addressable registers under conditions defined by the bits in said second bit fields, and means for transferring said formed addresses to said stack register addressing means whereby stack registers are selected for storing addresses of operands computed from address date in said re-fetched non-directly executable instruction during simulated execution thereof.