US4027262A
Expired / Lapsed
US
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Phase detector employing quadruple memory elements
Assignee: Bendix Corp
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Filing: 1976-03-02
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Granted: 1977-05-31
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Expires: 1996-03-02
Abstract
Abstract A phase detector which employs four memory elements suitably comprised by D-type flip-flops. The detector provides an output dependent upon the phase difference between two input signals. One pair of memory elements is clocked by one input signal. The other pair of memory elements is clocked by the other input signal. The memory elements are so arranged that when the ratio of the frequencies of the input signals is less than 2:1, the detector provides three output states which may be used in a phase locked oscillator to cause, in the first state, an increase in the frequency of one input signal; in the second state, no frequency change; and in the third state, a decrease in frequency. Above a frequency ratio of 2:1, the detector never enters the second state. Elimination of the second state under such conditions decreases the time required for a phase locked oscillator with this detector to achieve phase lock.
Inventors
- 👤 Claude A. Sharpe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:58
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03K; H03K5/00; H03K5/22; H03K5/26; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
281 words
In a phase detector which includes a pair of preconditionable, resettable, clock pulse operated memory elements for comparing the phase of two input signals, one such signal providing clock pulses for one said memory element, the other such signal providing clock pulses for the other said memory element, the outputs of said memory elements constituting the phase detector outputs, the improvement comprising an additional pair of preconditionable, clock pulse operated memory elements; means applying the output of one of said memory elements of said first-named pair to precondition one of said memory elements of said additional pair; means applying one said input signal as clock pulses both to the one of said additional pair of memory elements and to the one of said first-named pair of memory elements serving to precondition said one of said additional pair of memory elements; means combining the output of said one of said first-named pair of memory elements with the output of said one of said additional pair of memory elements, said combined outputs constituting one output of the improved phase detector; means applying the output of the other of said memory elements of said first-named pair to precondition the other of said memory elements of said additional pair; means applying the other said input signal as clock pulses both to the other of said memory elements of said additional pair and to the other of said first-named pair of memory elements; and means combining the output of the other of said memory elements of said additional pair with the output of the other of said memory elements of said first-named pair, said last-named combined outputs constituting the other output of the improved phase detector.
Claim 2
Dependent Claim
281 words
In a phase detector which includes a pair of preconditionable, resettable, clock pulse operated memory elements for comparing the phase of two input signals, one such signal providing clock pulses for one said memory element, the other such signal providing clock pulses for the other said memory element, the outputs of said memory elements constituting the phase detector outputs, the improvement comprising an additional pair of preconditionable, clock pulse operated memory elements; means applying the output of one of said memory elements of said first-named pair to precondition one of said memory elements of said additional pair; means applying one said input signal as clock pulses both to the one of said additional pair of memory elements and to the one of said first-named pair of memory elements serving to precondition said one of said additional pair of memory elements; means combining the output of said one of said first-named pair of memory elements with the output of said one of said additional pair of memory elements, said combined outputs constituting one output of the improved phase detector; means applying the output of the other of said memory elements of said first-named pair to precondition the other of said memory elements of said additional pair; means applying the other said input signal as clock pulses both to the other of said memory elements of said additional pair and to the other of said first-named pair of memory elements; and means combining the output of the other of said memory elements of said additional pair with the output of the other of said memory elements of said first-named pair, said last-named combined outputs constituting the other output of the improved phase detector.
Claim 3
Dependent Claim
35 words
The improved phase detector as claimed in claim 1 wherein each said memory element of said first-named pair and said additional pair is comprised by a flip-flop operating in an edge triggered type D mode.
Claim 4
Dependent Claim
24 words
The improved phase detector as claimed in claim 1 wherein both said output combining means each comprises a logic gate of the OR type.
Claim 5
Dependent Claim
289 words
A phase detector for use in phase locked oscillators, and the like, providing an output dependent upon the relative phase of two input signals, comprising four memory elements, each of said memory elements having a clock input, a precondition input and an output, said output assuming the valve present at said precondition input upon the appearance of signal at said clock input and retaining such value after disappearance of signal at said clock input, at least two of said memory elements having reset means for removing output retained by that memory element; a first pair of said memory elements, at least one of which includes reset means, receiving at said clock inputs thereof one of the signals whose phase is to be detected; a second pair of said memory elements; at least one of which includes reset means receiving at said clock inputs thereof the other of the signals whose phase is to be detected; means applying a signal of constant value to said precondition inputs to each said memory element having reset means; means in each said first pair and said second pair of memory elements applying the output of said memory element having reset means to said precondition input of the remaining memory element of that pair; logic means combining the outputs of said memory elements having reset means and providing signal to said reset means whenever said combined outputs are logically true for the logic AND operation; means for combining the outputs of both said memory elements of said first pair to provide a detector output of a first state; and means for combining and inverting the outputs of both said memory elements of said second pair to provide a detector output of a second state.
Claim 6
Dependent Claim
289 words
A phase detector for use in phase locked oscillators, and the like, providing an output dependent upon the relative phase of two input signals, comprising four memory elements, each of said memory elements having a clock input, a precondition input and an output, said output assuming the valve present at said precondition input upon the appearance of signal at said clock input and retaining such value after disappearance of signal at said clock input, at least two of said memory elements having reset means for removing output retained by that memory element; a first pair of said memory elements, at least one of which includes reset means, receiving at said clock inputs thereof one of the signals whose phase is to be detected; a second pair of said memory elements; at least one of which includes reset means receiving at said clock inputs thereof the other of the signals whose phase is to be detected; means applying a signal of constant value to said precondition inputs to each said memory element having reset means; means in each said first pair and said second pair of memory elements applying the output of said memory element having reset means to said precondition input of the remaining memory element of that pair; logic means combining the outputs of said memory elements having reset means and providing signal to said reset means whenever said combined outputs are logically true for the logic AND operation; means for combining the outputs of both said memory elements of said first pair to provide a detector output of a first state; and means for combining and inverting the outputs of both said memory elements of said second pair to provide a detector output of a second state.
Claim 7
Dependent Claim
25 words
A phase detector as claimed in claim 4 wherein said memory elements comprise flip-flops, each said flip-flop operating in an edge triggered type D mode.
Claim 8
Dependent Claim
34 words
A phase detector as claimed in claim 4 wherein each said means for combining the outputs of said memory elements of said first and second pairs comprises a logic gate of the OR type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-30 | 1980-11-29 | 1981-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-30 | 1984-11-29 | 1985-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-30 | 1988-11-29 | 1989-05-31 | $7700.00 | Window Closed / Lapsed |