US4027173A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate circuit
Assignee: Hitachi Ltd
•
Filing: 1975-11-21
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Granted: 1977-05-31
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Expires: 1995-11-21
Abstract
Abstract An input gate circuit of a semiconductor integrated circuit composed of insulated gate field-effect transistors, comprises a driving transistor and a load transistor which form an inverter, a transistor which prevents the input of the integrated circuit from being opened, and resistance means to protect the transistors. A first resistance is connected in series between an input terminal and the gate of the driving transistor, while another resistance is connected between the input terminal and one end of the input opening preventing transistor whose other end is connected to a power supply terminal.
Inventors
- 👤 Kosei Nomiya
- 👤 Tadao Kikuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
138 words
In a semiconductor integrated circuit comprising: first and second field-effect transistors having their source and drain terminals connected in series between first and second reference voltage terminals; an output terminal connected to said first and second field-effect transistors; an input terminal to which a voltage input signal is applied; a first resistor connected between said input terminal and the gate of said second transistor for protecting the gate of said second field-effect transistor from dielectric breakdown-inducing high voltage surges applied at said input terminal; and a third field effect transistor coupled between said second reference voltage terminal and said input terminal; the improvement comprising: a second resistor connected between said third field effect transistor and said input terminal for suppressing noise voltage surges applied at said input terminal and thereby providing protection for said third field effect transistor.
Claim 2
Dependent Claim
138 words
In a semiconductor integrated circuit comprising: first and second field-effect transistors having their source and drain terminals connected in series between first and second reference voltage terminals; an output terminal connected to said first and second field-effect transistors; an input terminal to which a voltage input signal is applied; a first resistor connected between said input terminal and the gate of said second transistor for protecting the gate of said second field-effect transistor from dielectric breakdown-inducing high voltage surges applied at said input terminal; and a third field effect transistor coupled between said second reference voltage terminal and said input terminal; the improvement comprising: a second resistor connected between said third field effect transistor and said input terminal for suppressing noise voltage surges applied at said input terminal and thereby providing protection for said third field effect transistor.
Claim 3
Dependent Claim
27 words
The improvement according to claim 1, further comprising a third resistor connected between the gate of said third field effect transistor and a third reference voltage terminal.
Claim 4
Dependent Claim
21 words
The improvement according to claim 2, wherein the gate of said first transistor is connected to said third reference voltage terminal.
Claim 5
Dependent Claim
23 words
The improvement according to claim 1, wherein said second resistor is connected between the source of said third transistor and said input terminal.
Claim 6
Dependent Claim
27 words
The improvement according to claim 4, further comprising a third resistor connected between the gate of said third field effect transistor and a third reference voltage terminal.
Claim 7
Dependent Claim
21 words
The improvement according to claim 5, wherein the gate of said first transistor is connected to said third reference voltage terminal.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-30 | 1980-11-29 | 1981-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-30 | 1984-11-29 | 1985-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-30 | 1988-11-29 | 1989-05-31 | $7700.00 | Window Closed / Lapsed |