Patent US4025762A successfully refreshed from Google Patents.
US4025762A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reference signal circuit
Assignee: General Electric Co
•
Filing: 1975-11-21
•
Granted: 1977-05-24
•
Expires: 1995-11-21
Abstract
Abstract In a prime mover control system, control over the prime mover is dependent, in part, upon the validity of a reference signal to the control system. Circuitry is provided between a reference signal generator and the control system whereby under normal conditions the reference signal to the control system is the same as the output of the reference signal generator. However, if the reference signal generator output becomes invalid, then a stored reference signal may be substituted for the reference signal generator output by switching from a first signal channel to an alternate second signal channel, each channel selectably interconnecting the reference signal generator and the control system. The output of the second signal channel is periodically updated to follow, with a time lag, the reference signal generator output except when an invalid reference signal generator output is detected whereupon the update of the second signal channel is frozen at a last valid reference signal which is then input into the control system.
Inventors
- 👤 Anthony J. Rossi
- 👤 Donald F. Behringer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:44
CPC Classifications
F; F01; F01D; F01D17/00; F01D17/20; F01D17/22; F01D17/24; G; G05; G05B; G05B9/00; G05B9/02; H; H02; H02P; H02P23/00; H02P23/16
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
224 words
In a prime mover control system, a reference signal is input into the control system through a reference signal circuit, the reference signal circuit including a signal storage means; the reference signal circuit having an input end connected to a reference signal generator and an output end connected to the control system; the output end following the input end except when the input end becomes invalid whereupon the output end follows the signal storage means, the reference signal circuit comprising: a first signal channel connected to the input end of the reference signal circuit; a second alternate signal channel, including the signal storage means, connected to the input end of the reference signal circuit; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the input update signal and the output update signal having a time lag therebetween; and, switching means connected to the first and second channels and to the signal update means; the switching means connecting the first channel to the reference signal circuit output end except when the input end becomes invalid whereupon the switching means connects the second channel to the reference signal circuit output end and interrupts the signal update means whereby the reference signal circuit output end follows the last output of the signal storage means.
Claim 2
Dependent Claim
224 words
In a prime mover control system, a reference signal is input into the control system through a reference signal circuit, the reference signal circuit including a signal storage means; the reference signal circuit having an input end connected to a reference signal generator and an output end connected to the control system; the output end following the input end except when the input end becomes invalid whereupon the output end follows the signal storage means, the reference signal circuit comprising: a first signal channel connected to the input end of the reference signal circuit; a second alternate signal channel, including the signal storage means, connected to the input end of the reference signal circuit; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the input update signal and the output update signal having a time lag therebetween; and, switching means connected to the first and second channels and to the signal update means; the switching means connecting the first channel to the reference signal circuit output end except when the input end becomes invalid whereupon the switching means connects the second channel to the reference signal circuit output end and interrupts the signal update means whereby the reference signal circuit output end follows the last output of the signal storage means.
Claim 3
Dependent Claim
73 words
The circuit recited in claim 1 wherein the signal storage means comprises: a digital counter connected to the input end of the reference signal circuit and actuated by the storage input update signal; and, a digital shift register connected to the output of the digital counter and actuated by the storage output update signal whereby information stored on the input of the shift register is transferred to the output of the shift register.
Claim 4
Dependent Claim
24 words
The circuit recited in claim 2 wherein the signal storage means further includes an analog to digital converter in combination with said digital counter.
Claim 5
Dependent Claim
63 words
The circuit recited in claim 1 wherein said signal update means comprise: clock means providing a pulse train output; phase shifter means connected to the clock means providing Q and Q outputs; a first monostable multivibrator connected to the Q output for providing an input update signal; and, a second monostable multivibrator connected to the Q output for providing an output update signal.
Claim 6
Dependent Claim
15 words
The circuit recited in claim 4 wherein the phase shifter means is a J-K flip-flop.
Claim 7
Dependent Claim
83 words
The circuit recited in claim 1 wherein said switching means comprise: a first switch interconnecting the first channel with the reference signal circuit output end; a second switch interconnecting the second channel with the reference signal circuit output end; a third switch interconnecting the signal update means with a voltage source; relay means associated with the switches for selectively closing the first and third switches and opening the second switch and for opening the first and third switches and closing the second switch.
Claim 8
Dependent Claim
187 words
A reference signal circuit for a control system, including a signal storage means, having an output end which follows an input end except when the input end becomes invalid whereupon the output end follows the signal storage means, the reference signal circuit comprising: a first signal channel connected to the input end of the reference signal circuit; a second alternate signal channel including the signal storage means connected to the input end of the reference signal circuit; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the input update signal and the output update signal having a time lag therebetween; and, switching means connected to the first and second channels and to the signal update means; the switching means connecting the first signal channel to the reference signal circuit output end except when the input end becomes invalid whereupon the switching means connects the second channel to the memory circuit output end and interrupts the signal update means whereby the reference signal circuit output end follows the last output of the signal storage means.
Claim 9
Dependent Claim
187 words
A reference signal circuit for a control system, including a signal storage means, having an output end which follows an input end except when the input end becomes invalid whereupon the output end follows the signal storage means, the reference signal circuit comprising: a first signal channel connected to the input end of the reference signal circuit; a second alternate signal channel including the signal storage means connected to the input end of the reference signal circuit; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the input update signal and the output update signal having a time lag therebetween; and, switching means connected to the first and second channels and to the signal update means; the switching means connecting the first signal channel to the reference signal circuit output end except when the input end becomes invalid whereupon the switching means connects the second channel to the memory circuit output end and interrupts the signal update means whereby the reference signal circuit output end follows the last output of the signal storage means.
Claim 10
Dependent Claim
142 words
A reference signal circuit having an input end and an output end, said circuit comprising: a first signal channel connected to the input end; a second alternate signal channel including a signal storage means connected to the input end; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the storage output update signal lagging the storage input update signal; switching means for selectably connecting the first and second channels to said output end; said switching means having a first mode wherein the first channel is connected to the circuit output and a second mode wherein the second channel is connected to the circuit output whereby in the first mode the circuit output follows the circuit input and in the second mode the circuit output follows the signal storage means.
Claim 11
Dependent Claim
142 words
A reference signal circuit having an input end and an output end, said circuit comprising: a first signal channel connected to the input end; a second alternate signal channel including a signal storage means connected to the input end; signal update means connected to the signal storage means for providing a storage input update signal and a storage output update signal, the storage output update signal lagging the storage input update signal; switching means for selectably connecting the first and second channels to said output end; said switching means having a first mode wherein the first channel is connected to the circuit output and a second mode wherein the second channel is connected to the circuit output whereby in the first mode the circuit output follows the circuit input and in the second mode the circuit output follows the signal storage means.
Claim 12
Dependent Claim
36 words
The circuit recited in claim 8 wherein said switching means is connected to said signal update means whereby in the second mode the signal update means is stopped and the signal storage means output becomes fixed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-23 | 1980-11-22 | 1981-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-23 | 1984-11-22 | 1985-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-23 | 1988-11-22 | 1989-05-24 | $7700.00 | Window Closed / Lapsed |