Electronic clock with capacitative resetting

Claim 1

An electronic clock comprising a decade seconds counter, a sexenary tens-of-seconds counter, a decade minutes counter, a sexenary tens-of-minutes counter, an hours counter and a tens-of-hours counter, all the counters being cascade-connected and, except for the seconds counter, receiving as stepping-on pulses the carry pulses of the previous counter, means for deriving from a frequency source timing pulses at a repetition frequency higher than 1 Hz, a frequency-divider chain receiving the timing pulses and supplying resetting pulses at a lower frequency than said frequency source and the seconds counter coupled to said frequency divider chain to receive pulses at the frequency of 1 Hz, capacitative resetting control keys, transistors having input circuits respectively containing capacitative resetting keys and output circuits, resettable monostable circuits in the output circuits of said transistors, AND-gates receiving the resetting pulses and the output signals of said resettable monostable circuits and OR-gates disposed between the counters and receiving the stepping-on pulses of the counter and the output pulses of the AND-gates.