Reset system for digital electronic timepiece

Claim 2

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequencydivider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a base signal source for developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: first reset switching means, connected to tHe first order display decoder register, actuation of said first reset switching means setting said first order display to zero, regardless of the condition of said display at the instant said first reset switching means is actuated, and simultaneously inhibiting transmission of actuating signals to the succeeding displays in said timepiece; and second reset switching means, connected to said base signal input source and to the decoder registers in the higher order displays of said timepiece, for applying said base signal directly to each higher order display decoder register, individually, to advance the higher order displays.

Claim 3

A reset system for a digital electronic timepiece, as set forth in claim 1, in which said first reset switching means is connected to the decoder registers in both the first and second order displays to set both to zero without changing any of the higher order displays.

Claim 4

A reset system for a digital electronic timepiece, as set forth in claim 2, in which said first reset switching means comprises a two-pole normally closed momentary-actuation switch, each pole individually connected to a single stage in a respective one of the decoder registers in said first and second order displays.

Claim 5

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a base signal source developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: first reset switching means, connected to the first and second order display decoder registers, actuation of said first reset switching means setting said first and second order displays to zero regardless of the condition of said displays at the instant said first reset switching means is actuated, and simultaneously inhibiting transmission of actuating signals to the succeeding displays in said timepiece; second reset switching means, connected to said base signal input circuit and to the decoder registers in the higher order displays of said timepiece, for applying said base signal directly to each higher order display decoder register, individually, to advance the higher order displays, said second reset switching means comprising a plurality of momentary-actuation normally open reset switches, each connected from said base signal input source to a single stage of a respective one of said higher order decoder registers, a reset signal source developing a high-speed reset signal having a frequency substantially higher than said base signal frequency, and a set rate selector switch, for connecting said reset switches to either said base signal circuit for resetting at a normal rate or to said reset signal source for resetting at a high speed rate.

Claim 6

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a base signal source developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: first reset switching means, connected to the first and second order display decoder registers, actuation of said first reset switching means setting said first and second order displays to zero regardless of the condition of said displays at the instant said first reset switching means is actuated, and simultaneously inhibiting transmission of actuating signals to the succeeding displays in said timepiece; second reset switching means, connected to said base signal input circuit and to the decoder registers in the higher order displays of said timepiece, for applying said base signal directly to each higher order display decoder register, individually, to advance the higher order displays, said second reset switching means comprising a plurality of momentary-actuation normally open reset switches, each connected from said base signal input source to a single stage of a respective one of said higher order decoder registers, a reset signal source developing a high-speed reset signal having a frequency substantially higher than said base signal frequency, and a set rate selector switch, for connecting said reset switches to either said base signal circuit for resetting at a normal rate or to said reset signal source for resetting at a high speed rate.

Claim 7

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a 1 Hertz base signal source developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: first reset switching means, connected to the first and second order display decoder registers, actuation of said first reset switching means setting said first and second order displays to zero and simultaneously inhibiting transmission of actuating signals to the succceeding displays in said timepiece; Second reset switching means, connected to said base signal input source and to the decoder registers in the higher order displays of said timepiece, for applying said base signal directly to each higher order display decoder register, individually, to advance the higher order displays, a 60 Hertz signal source, and switch means for connecting the first order display to said 60 Hertz signal source for operation of said timepiece as a high-accuracy timer.

Claim 8

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a 1 Hertz base signal source developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: first reset switching means, connected to the first and second order display decoder registers, actuation of said first reset switching means setting said first and second order displays to zero and simultaneously inhibiting transmission of actuating signals to the succceeding displays in said timepiece; Second reset switching means, connected to said base signal input source and to the decoder registers in the higher order displays of said timepiece, for applying said base signal directly to each higher order display decoder register, individually, to advance the higher order displays, a 60 Hertz signal source, and switch means for connecting the first order display to said 60 Hertz signal source for operation of said timepiece as a high-accuracy timer.

Claim 9

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a base signal source for developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: control means included in at least said first order decoder register and responsive to the application of a single voltage change from a first level to a second level to (a) reset said first order display to a predetermined display condition regardless of the display condition thereof at the instant said voltage change occurs and (b) simultaneously inhibit the application of actuating signals to successive higher decoder registers in said timepiece for the duration of said second voltage level, a reset switching means coupled between said control means and a voltage source for conditionally changing the voltage level of said control means from said first level to said second level so as to permit the individual change of successively higher decoder registers during the period said second voltage level is applied to said control means.

Claim 10

A reset system for a digital electronic timepiece of the kind comprising a series of individual displays for time intervals of successively higher order, each display including a frequency-divider decoder register for driving the display and for supplying an actuating signal to the decoder register in the display of the next higher order, said timepiece further comprising a base signal source for developing a base signal of stable frequency, and a base signal input circuit for applying the base signal to the decoder register in the first order display, said reset system comprising: control means included in at least said first order decoder register and responsive to the application of a single voltage change from a first level to a second level to (a) reset said first order display to a predetermined display condition regardless of the display condition thereof at the instant said voltage change occurs and (b) simultaneously inhibit the application of actuating signals to successive higher decoder registers in said timepiece for the duration of said second voltage level, a reset switching means coupled between said control means and a voltage source for conditionally changing the voltage level of said control means from said first level to said second level so as to permit the individual change of successively higher decoder registers during the period said second voltage level is applied to said control means.

Claim 11

Apparatus according to claim 6 wherein said predetermined display condition of first order decoder register is zero.

Claim 12

Apparatus according to claim 6 wherein additional reset switching means are coupled between said base signal source and the decoder registers in the higher order displays of said timepiece for conditionally applying said base signal directly to selected ones of said individual higher order display decoder registers for selectively advancing any given higher order display at a rate faster than that produced by the supply of the actuating signal to the decoder register of that display from the decoder register of the next lower order register, during the period said second voltage level is applied to said control means.

Claim 13

Apparatus according to claim 6 wherein is provided a secondary source providing a signal at a frequency higher than that of said base signal source, and additional switching means whereby a signal from said secondary source or a signal from said base signal source may be selectively applied to any one of the higher order displays during the period said second voltage level is applied to said control means.