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Automatic scaled digital integrator

Assignee: United States Department of the Navy
•
Filing: 1974-09-23
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Granted: 1977-05-10
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Expires: 1994-09-23
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Abstract

Abstract A digital scaler adjusts the processing of an input signal to a digital fback integrator by a multiplying technique which is implemented by shifting the connections between an analog-to-digital converter and the input to an adder, both forming the input section of a digital feedback integrator, in order to maintain a constant dynamic range of the output signal.

Inventors

  • 👤 Lawrence M. Leibowitz
  • 👤 Phillip L. Watkins

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 06:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F17/00; G06F17/10; G06F17/18; G06J; G06J1/00

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 51 words
In a digital integrator device having input signal conditioning means and signal integrating means, the improvement comprising: signal multiplying means for adjusting the magnitude of an input signal in accordance with the number of signals to be integrated, said multiplying means being connected between said conditioning means and said integrating means.
Claim 2
Dependent Claim 51 words
In a digital integrator device having input signal conditioning means and signal integrating means, the improvement comprising: signal multiplying means for adjusting the magnitude of an input signal in accordance with the number of signals to be integrated, said multiplying means being connected between said conditioning means and said integrating means.
Claim 3
Dependent Claim 49 words
The digital integrator device of claim 1 wherein said multiplying means multiplies the input signal to said device by the factor 2 n .sbsp.m.sbsp.a.sbsp.x -n wherein 2 n is the number of samples to be integrated and 2 n .sbsp.m.sbsp.a.sbsp.x is the maximum number of samples to be integrated.
Claim 4
Dependent Claim 14 words
The digital integrator of claim 2 wherein said multiplying means is a binary multiplier.
Claim 5
Dependent Claim 16 words
The digital integrator of claim 3 wherein said binary multiplier is comprised of a switching network.
Claim 6
Dependent Claim 15 words
The digital integrator of claim 4 wherein said signal conditioning means is an analog-to-digital converter.

References Cited (Backward Citations)

US3479592A Cited
US3422435A Cited
US3653015A Cited
US3796952A Cited
US3783392A Cited
US3851160A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-05-09 1980-11-08 1981-05-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-05-09 1984-11-08 1985-05-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-05-09 1988-11-08 1989-05-10 $7700.00 Window Closed / Lapsed

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