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US4022930A Expired / Lapsed US ⏱️ 0.0 years remaining

Multilevel metallization for integrated circuits

Assignee: AT&T Inc
•
Filing: 1975-05-30
•
Granted: 1977-05-10
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Expires: 1995-05-30
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Abstract

Abstract The specification describes a procedure for multilevel metallization of semiconductor integrated circuits in which the severity of the step formed by the edges of the first level pattern and the intermediate insulator over which the second level metallization pattern extends is reduced by beveling the edge. The bevel occurs during selective etching of the first level metal as a consequence of depositing the first level metal over a range of diminishing temperatures. Metal layers, notably aluminum, deposited in this way exhibit a differential etch rate such that the layer etches more slowly as etching proceeds through the thickness of the layer. Bevels of the order of 30° to the horizontal can be produced in this way.

Inventors

  • 👤 David Bruce Fraser

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 04:08
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/262; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; Y; Y10; Y10S; Y10S438/00; Y10S438/978

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 101 words
A method for producing multilevel metallization on a semiconductor substrate comprising, forming an insulating layer on the semiconductor wafer, forming an Al, Si or Al--Si metal layer over the insulating layer by depositing the metal while simultaneously decreasing the temperature of the semiconductor wafer, applying an etch resist pattern to the metal layer, and chemically etching away the regions of the metal layer exposed through the etch resist pattern to form a first level metallization pattern having beveled edges, forming a second insulating layer over the first level metallization pattern, forming a second level metallization pattern on the second insulating layer.
Claim 2
Independent Claim 101 words
A method for producing multilevel metallization on a semiconductor substrate comprising, forming an insulating layer on the semiconductor wafer, forming an Al, Si or Al--Si metal layer over the insulating layer by depositing the metal while simultaneously decreasing the temperature of the semiconductor wafer, applying an etch resist pattern to the metal layer, and chemically etching away the regions of the metal layer exposed through the etch resist pattern to form a first level metallization pattern having beveled edges, forming a second insulating layer over the first level metallization pattern, forming a second level metallization pattern on the second insulating layer.
Claim 3
Dependent Claim 20 words
The method of claim 2 in which the wafer is silicon and the metal is aluminum or an aluminum-silicon alloy.
Claim 4
Dependent Claim 16 words
The method of claim 1 in which the wafer is silicon and the metal is polysilicon.
Claim 5
Dependent Claim 18 words
The method of claim 1 in which the decreasing temperature range extends between approximately 350° and room temperature.

References Cited (Backward Citations)

US3413157A Cited
US3620837A Cited
US3579375A Cited
US3672983A Cited
US3806361A Cited
US3825454A Cited
US3801477A Cited
US3855112A Cited
US3909925A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-05-09 1980-11-08 1981-05-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-05-09 1984-11-08 1985-05-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-05-09 1988-11-08 1989-05-10 $7700.00 Window Closed / Lapsed

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