US4021704A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase sequence correcting system for three-phase AC power
Assignee: York International Corp
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Filing: 1976-02-27
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Granted: 1977-05-03
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Expires: 1996-02-27
Abstract
Abstract The phase sequence of a three-phase AC power supply is detected and information representing that sequence is stored in a memory device, such as a flip-flop. Since the power supply, once it is energized, may require a few seconds to stabilize (such as may be the case when the power source is a diesel generator), the information fed to the memory device is likely to change during the stabilizing period. At the end of that period, however, the stored information represents the true phase sequence of the AC power supply, and at that time the information is read out and used to actuate switching apparatus to interconnect the three-phase AC power supply to the three terminals of a phase-sensitive load (such as a three-phase AC motor) in the manner necessary to provide the load with a desired phase rotation sequence. After the stabilizing period, the input circuitry of the memory device is inhibited so that the stored information representing the true phase sequence will be locked into the memory device and so that the device will be insensitive to any fluctuating voltages, frequency or noise that could otherwise cause an accidental phase reversal while the load is energized.
Inventors
- 👤 Dean K. Norbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:05
CPC Classifications
H; H02; H02H; H02H11/00; H02H11/004; F; F02; F02B; F02B3/00; F02B3/06
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
A phase sequence correcting system for coupling a three-terminal, three-phase AC power supply to a three-terminal, phase-sensitive load to apply three-phase power to the load in a desired rotation sequence, comprising: phase sequence sensing means for detecting the phase rotation sequence of the three-phase AC power supply; a memory device; write-in means, responsive to said sensing means, for actuating said memory device to store information therein representing the phase sequence of the AC power supply; inhibiting means for inhibiting the operation of said write-in means, when a predetermined time delay interval has elapsed after the system has been rendered operable, in order to lock the stored phase sequence information in said memory device; read-out means for reading out the stored phase sequence information from said memory device; and switching means, responsive to said read-out means, for interconnecting the three terminals of the three-phase AC power supply to the three terminals of the load in accordance with the interconnection pattern required to provide the load with the desired phase sequence.
Claim 2
Dependent Claim
169 words
A phase sequence correcting system for coupling a three-terminal, three-phase AC power supply to a three-terminal, phase-sensitive load to apply three-phase power to the load in a desired rotation sequence, comprising: phase sequence sensing means for detecting the phase rotation sequence of the three-phase AC power supply; a memory device; write-in means, responsive to said sensing means, for actuating said memory device to store information therein representing the phase sequence of the AC power supply; inhibiting means for inhibiting the operation of said write-in means, when a predetermined time delay interval has elapsed after the system has been rendered operable, in order to lock the stored phase sequence information in said memory device; read-out means for reading out the stored phase sequence information from said memory device; and switching means, responsive to said read-out means, for interconnecting the three terminals of the three-phase AC power supply to the three terminals of the load in accordance with the interconnection pattern required to provide the load with the desired phase sequence.
Claim 3
Dependent Claim
42 words
A phase sequence correcting system according to claim 1 wherein said inhibiting means includes a timer which begins to operate when the system is turned on and produces a control signal to effect inhibiting after said predetermined time delay interval has elapsed.
Claim 4
Dependent Claim
53 words
A phase sequence correcting system according to claim 1 wherein said memory device is a flip-flop which may be operated between its two operating states until said inhibiting means operates, whereupon said flip-flop is locked in the operating state in which it was established just prior to the operation of said inhibiting means.
Claim 5
Dependent Claim
85 words
A phase sequence correcting system according to claim 3 in which said flip-flop is actuated, by said write-in means, to a predetermined one of its two states when the desired phase sequence exists at the three-phase AC power supply and to the opposite state when the undesired phase sequence is present, and wherein said switching means includes a pair of contactors one of which is actuated when said one operating state is read-out and the other contactor actuating when the opposite operating state is read-out.
Claim 6
Dependent Claim
240 words
A phase sequence correcting system according to claim 1 in which said write-in means includes first and second NOR gates, an input of said first gate receiving a logic "0" signal when the desired phase sequence exists at the AC power supply and a logic "1" signal when the undesired phase sequence prevails, and an input of said second gate receiving a logic "1" signal when the desired phase sequence is present and a logic "0" signal when the undesired phase sequence occurs; in which said memory device is an R-S flip-flop having its set input connected to the output of said first NOR gate and its reset input connected to the output of said second NOR gate; said flip-flop being actuated, prior to the operation of said inhibiting means, to its set operating state by said first NOR gate when the desired phase sequence exists at the AC power supply and to its reset operating state by said second NOR gate when the undesired phase sequence is present; and in which said inhibiting means applies logic "1" signals to the other inputs of said first and second NOR gates in order to produce logic "0" signals for application to both the set and reset inputs of said flip-flop, thereby locking said flip-flop in the particular state in which it was established immediately prior to the application of the logic "1" signals to said NOR gate from said inhibiting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-02 | 1980-11-01 | 1981-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-02 | 1984-11-01 | 1985-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-02 | 1988-11-01 | 1989-05-03 | $7700.00 | Window Closed / Lapsed |