Incrementally adjustable digital attenuator/amplifier

Claim 2

In a pulse code modulation system wherein analog signal levels are represented by binary words encoded according to a predetermined law and resulting in a possibility of 2 n coded words for signals of each polarity, the system comprising a memory means having at least a storage capacity for 2 n memory words, each one having an address corresponding to a respective one of said coded words and each one representing X db of signal level variation relative to its corresponding coded word, a method of providing incrementally adjustable variation of signal levels, comprising the steps of: addressing said memory means with one of said coded words; and circulating said one of said coded words through the memory means a predetermined number of times M, a first memory address being defined by said one of said coded words and every subsequent address being defined by the memory word read out in the previous memory cycle, whereby the output from the memory means on termination of the last pass therethrough is a coded word representing MX db of signal level variation relative to said one of said coded words.

Claim 3

A circuit for providing incrementally adjustable variation of signal levels in a pulse code modulation system wherein analog signal levels are represented by binary words encoded according to a predetermined law and resulting in a possibility of 2 n coded words for signals of each polarity, comprising: memory means having at least a storage capacity for 2 n memory words, each one having an address corresponding to a respective one of said coded words and each one representing X db of signal level variation relative to its corresponding coded word; an interface circuit adapted to selectively receive serial and parallel data and to selectively output serial and parallel data, said interface circuit having its parallel input connected to the output of the memory means and its parallel output connected to the address input of the memory means; control means for effecting the loading of said interface circuit with one of said coded words, and for enabling the memory means to be addressed at the location defined by said coded word; said control means including means for effecting the circulation of said one of said coded words through the memory means via said interface circuit a predetermined number of times M, a first memory address being defined by said one of said coded words and every subsequent address being defined by the memory word read out in the previous memory cycle, whereby the output from the memory means on termination of the last pass therethrough is a coded word representing MX db of signal level variation relative to said one of said coded words.

Claim 4

A circuit for providing incrementally adjustable variation of signal levels in a pulse code modulation system wherein analog signal levels are represented by binary words encoded according to a predetermined law and resulting in a possibility of 2 n coded words for signals of each polarity, comprising: memory means having at least a storage capacity for 2 n memory words, each one having an address corresponding to a respective one of said coded words and each one representing X db of signal level variation relative to its corresponding coded word; an interface circuit adapted to selectively receive serial and parallel data and to selectively output serial and parallel data, said interface circuit having its parallel input connected to the output of the memory means and its parallel output connected to the address input of the memory means; control means for effecting the loading of said interface circuit with one of said coded words, and for enabling the memory means to be addressed at the location defined by said coded word; said control means including means for effecting the circulation of said one of said coded words through the memory means via said interface circuit a predetermined number of times M, a first memory address being defined by said one of said coded words and every subsequent address being defined by the memory word read out in the previous memory cycle, whereby the output from the memory means on termination of the last pass therethrough is a coded word representing MX db of signal level variation relative to said one of said coded words.

Claim 5

A circuit as defined in claim 2 wherein said memory means is a read-only memory.

Claim 6

A circuit for providing incrementally adjustable variation of signal levels in a pulse code modulation system wherein analog signal levels are represented by binary words encoded according to a predetermined law and resulting in a possibility of 2 n coded words for signals of each polarity, comprising: memory means having at least a storage capacity for 2 n memory words, each one having an address corresponding to a respective one of said coded words and each one representing X db of signal level variation relative to its corresponding coded word; an interface circuit having at least n storage locations; control means for effecting the loading of said interface circuit with one of said coded words, and for enabling the memory means to be addressed at the location defined by said coded word; a storage means for storing a first memory word located at the memory address defined by said coded word, the output of said storage means being connected to the input of the interface circuit and wherein said control means includes means for effecting the loading of said first memory word into said interface circuit, whereby said first memory word serves as the address of a second memory word which represents X db of signal level variation relative to the first memory word and 2X db of signal level variation relative to said one of said coded words.

Claim 7

A circuit for providing incrementally adjustable variation of signal levels in a pulse code modulation system wherein analog signal levels are represented by binary words encoded according to a predetermined law and resulting in a possibility of 2 n coded words for signals of each polarity, comprising: memory means having at least a storage capacity for 2 n memory words, each one having an address corresponding to a respective one of said coded words and each one representing X db of signal level variation relative to its corresponding coded word; an interface circuit having at least n storage locations; control means for effecting the loading of said interface circuit with one of said coded words, and for enabling the memory means to be addressed at the location defined by said coded word; a storage means for storing a first memory word located at the memory address defined by said coded word, the output of said storage means being connected to the input of the interface circuit and wherein said control means includes means for effecting the loading of said first memory word into said interface circuit, whereby said first memory word serves as the address of a second memory word which represents X db of signal level variation relative to the first memory word and 2X db of signal level variation relative to said one of said coded words.

Claim 8

A circuit as defined in claim 4 wherein the control means includes counter means responsive to signals from said control means for causing said one of said coded words to be circulated through the memory means a predetermined number of times M, whereby the output memory word represents MX db of signal level variation relative to said one of said coded words.

Claim 9

A circuit as defined in claim 4 wherein the interface circuit is a register matrix adapted to selectively receive serial and parallel data and to selectively output serial and parallel data in response to signals from the control means.

Claim 10

A circuit as defined in claim 4 wherein said memory means is a read-only-memory.