Integrated arithmetic unit for computing summed indexed products

Claim 2

An arithmetic unit suitable for large scale integration for computing summed indexed products comprising: 1. a vector adder for bit serial, word serial binary data containing sign and magnitude information, comprising: a. a first sign changing means to which serial binary data is applied from a first data input terminal (d 1 ) and subject to a first sign control input (c 1 ), b. a first serial summer to which two serial binary data streams are applied respectively from the output of said first sign changing means and from a second data input terminal (d 2 ), said summer producing a first output quantity (s 1 ) where s.sub.1 = (d.sub.2 ± d.sub.1) c. a second sign changing means to which serial binary data is applied from said first summer and subject to a second sign control input (c 2 ), d. a second serial summer to which two serial binary data streams are applied respectively from the output of said second sign changing means and from the output of a third data input terminal (d 3 ), said summer producing a second output quantity (s 2 ), where s.sub.2 = [d.sub.3 ± (d.sub.2 ± d.sub.1)] 2.

Claim 3

a vector multiplication logic for bit serial, word serial binary data, containing sign and magnitude information, comprising a. first multiplication means having a multiplicated input coupled to the output of said second serial summer and a multiplier input coupled to a fourth data input terminal (t 1 ), b. second multiplication means having a multiplicated input coupled to a fifth data input terminal (v 2 ), and to a multiplier input coupled to a sixth data input terminal (t 2 ), c. a third sign changing means to which serial binary data is applied from said first multiplication means and subject to a third sign control input (c 3 ), d. a fourth sign changing means to which serial binary data is applied from said second multiplication means and subject to a fourth sign control input (c 4 ), e. a third serial summer to which two serial binary data streams are applied respectively from the outputs of said third and fourth sign changing means, said third serial summer producing a third output quantity: ##EQU14## wherein the first sign selection in the expression is dependent on c 4 , the second sign selection is dependent on c 3 the third sign selection is dependent on c 2 , and

Claim 4

a vector multiplication logic for bit serial, word serial binary data, containing sign and magnitude information, comprising a. first multiplication means having a multiplicated input coupled to the output of said second serial summer and a multiplier input coupled to a fourth data input terminal (t 1 ), b. second multiplication means having a multiplicated input coupled to a fifth data input terminal (v 2 ), and to a multiplier input coupled to a sixth data input terminal (t 2 ), c. a third sign changing means to which serial binary data is applied from said first multiplication means and subject to a third sign control input (c 3 ), d. a fourth sign changing means to which serial binary data is applied from said second multiplication means and subject to a fourth sign control input (c 4 ), e. a third serial summer to which two serial binary data streams are applied respectively from the outputs of said third and fourth sign changing means, said third serial summer producing a third output quantity: ##EQU14## wherein the first sign selection in the expression is dependent on c 4 , the second sign selection is dependent on c 3 the third sign selection is dependent on c 2 , and

Claim 5

the fourth sign selection is dependent on c 1 . 2. An arithmetic unit as set forth in claim 1 wherein said vector adder accepts serial binary data inputs at said first (d 1 ), second (d 2 ) and third (d 3 ) data input terminals and produces serial binary data outputs in two's complement notation, least significant bit first in time and the sign bit last, and wherein said first and second sign changing means are each two's complementers.

Claim 6

An arithmetic unit as set forth in claim 2 wherein said vector multiplication logic multiplies numbers in serial binary data format to obtain products in serial binary data format: a. the multiplicand inputs of the first and second multiplication means accept sign and magnitude information in two's complement notation, least significant bit first in time and the sign bit last; b. the multiplier inputs of said first and second multiplication means accept magnitude-only information; and c. the products of said first and second multiplication means contain sign and magnitude data in two's complement notation, least significant bit first in time and the sign bit last.

Claim 7

An arithmetic unit as set forth in claim 3 wherein the third and fourth sign changing means are each two's complementers.

Claim 8

An arithmetic unit as set forth in claim 4 wherein: a. sign information associated with the multiplier input of said first multiplication means is applied to the control input (c 3 ) of said third sign changing means, and wherein b. sign information associated with the multiplier input of said second multiplication means is applied to the control input (c 4 ) of said fourth sign changing means.

Claim 9

An arithmetic unit as set forth in claim 5 wherein said first and second multiplication means yield single precision products, said multiplier, multiplicand and product bit streams occurring serially at equal word rates with the least significant bit first in time.

Claim 10

An arithmetic unit as set forth in claim 6 suitable for computing summed indexed products wherein the indexed quantities include products of signed data and trigonometric data terms containing orthogonal elememts; wherein the signed data is applied to the first (d 1 ), second (d 2 ), third (d 3 ) and fifth (v 2 ) data input terminals and the orthogonal trigonometric data is applied to the fourth (t 1 ) and sixth (t 2 ) data input terminals; said orthogonality reducing change in word length in the output of said third summer resulting from change in the trigonometric data, wherein a bit time of the word processing period is saved.

Claim 11

An arithmetic unit as set forth in claim 7 wherein each trigonometric data term is a sine and cosine of the same angle.

Claim 12

Apparatus for computing summed index products comprising a set of four arithmetic units (A r , A i , C r , C i ), each unit comprising: 1. a vector adder for bit serial, word serial binary data containing sign and magnitude information, comprising: a. a first sign changing means to which serial binary data is applied from a first data input terminal (d 1 ) and subject to a first sign control input (c 1 ), b. a first serial summer to which two serial binary data streams are applied respectively from the output of said first sign changing means and from a second data input terminal (d 2 ), said summer producing a first output quantity (s 1 ), where s.sub.1 = (d.sub.2 ± d.sub.1) c. a second sign changing means to which serial binary data is applied from said first summer and subject to a second sign control input (c 2 ), d. a second serial summer to which two serial binary data streams are applied respectively from the output of said second sign changing means and from the output of a third data input terminal (d 3 ), said summer producing a second output quantity (s 2 ), where s.sub.2 = [d.sub.3 ± (d.sub.2 ± d.sub.1)] 2. a vector multiplication logic for bit serial, word serial binary data, containing sign and magnitude information, comprising: a. first multiplication means having a multiplicand input coupled to the output of said second serial summer and a multiplier input coupled to a fourth data input terminal (t 1 ), b. second multiplication means having a multiplicand input coupled to a fifth data input terminal (v 2 ), and to a multiplier input coupled to a sixth data input terminal (t 2 ), c. a third sign changing means to which serial binary data is applied from said first multiplication means and subject to a third sign control input (c 3 ), d. a fourth sign changing means to which serial binary data is applied from said second multiplication means and subject to a fourth sign control input (c 4 ), e. a third serial summer to which two serial binary data streams are applied respectively from the outputs of said third and fourth sign changing means, said third serial summer producing a third output quantity Z: ##EQU15## said units being interconnected as follows: the s 1 output of A r (s 1Ar ) is coupled to the d 3 input of C r , and the s 1 output of C r (s 1Cr ) is coupled to the d 3 input of A r , the s 1 output of A i (s 1Ai ) is coupled to the d 3 input of C i , and the s 1 output of C i (s 1Ci ) is coupled to the d 3 input of A i , the s 2 output of A r (s 2Ar ) is coupled to the v 2 input of A i , and the s 2 output of A i (s 2Ai ) is coupled to the v 2 input of A r , the s 2 output of C r (s 2Cr ) is coupled to the v 2 input of C i , and the s 2 output of C i (s 2Ci ) is coupled to the v 2 input of C r , so as to provide the overall function of: ##EQU16## wherein d 1Ar , d 1Ai , d 1Cr , d 1Ci ; d 2Ar , d 2Ai , d 2Cr , d 2Ci ; d 3Ar , d 3Ai , d 3Cr , d 3Ci ; t 1Ar , t 1Ai , t 1Cr , t 1Ci ; v 2Ar , v 2Ai , v 2Cr , v 2Ci ; t 2Ar , t 2Ai , t 2Cr , t 2Ci denote the serial data inputs (d 1 , d 2 , d 3 , t 1 , v 2 , t 2 ) of the subscripted arithmetic units (A r , A i , C r C i ); wherein c 1Ar , c 1Ai , c 1Cr , c 1Ci ; c 2Ar , c 2Ai , c 2Cr , c 2Ci ; c 3Ar , c 3Ai , c 3Cr , c 3Ci ; c 4Ar , c 4Ai , c 4Cr c 4Ci denote the sign control settings (c 1 , c 2 , c 3 , c 4 ) applied to the subscripted arithmetic units (A r , A i , C r , C i ), and z Ar , z Ai , z Cr , z Ci ) denote the (z) serial data outputs of the subscripted arithmetic units (A r , A i , C r , C i ) as a function of the inputs and control settings.

Claim 13

Apparatus for computing summed index products comprising a set of four arithmetic units (A r , A i , C r , C i ), each unit comprising: 1. a vector adder for bit serial, word serial binary data containing sign and magnitude information, comprising: a. a first sign changing means to which serial binary data is applied from a first data input terminal (d 1 ) and subject to a first sign control input (c 1 ), b. a first serial summer to which two serial binary data streams are applied respectively from the output of said first sign changing means and from a second data input terminal (d 2 ), said summer producing a first output quantity (s 1 ), where s.sub.1 = (d.sub.2 ± d.sub.1) c. a second sign changing means to which serial binary data is applied from said first summer and subject to a second sign control input (c 2 ), d. a second serial summer to which two serial binary data streams are applied respectively from the output of said second sign changing means and from the output of a third data input terminal (d 3 ), said summer producing a second output quantity (s 2 ), where s.sub.2 = [d.sub.3 ± (d.sub.2 ± d.sub.1)] 2. a vector multiplication logic for bit serial, word serial binary data, containing sign and magnitude information, comprising: a. first multiplication means having a multiplicand input coupled to the output of said second serial summer and a multiplier input coupled to a fourth data input terminal (t 1 ), b. second multiplication means having a multiplicand input coupled to a fifth data input terminal (v 2 ), and to a multiplier input coupled to a sixth data input terminal (t 2 ), c. a third sign changing means to which serial binary data is applied from said first multiplication means and subject to a third sign control input (c 3 ), d. a fourth sign changing means to which serial binary data is applied from said second multiplication means and subject to a fourth sign control input (c 4 ), e. a third serial summer to which two serial binary data streams are applied respectively from the outputs of said third and fourth sign changing means, said third serial summer producing a third output quantity Z: ##EQU15## said units being interconnected as follows: the s 1 output of A r (s 1Ar ) is coupled to the d 3 input of C r , and the s 1 output of C r (s 1Cr ) is coupled to the d 3 input of A r , the s 1 output of A i (s 1Ai ) is coupled to the d 3 input of C i , and the s 1 output of C i (s 1Ci ) is coupled to the d 3 input of A i , the s 2 output of A r (s 2Ar ) is coupled to the v 2 input of A i , and the s 2 output of A i (s 2Ai ) is coupled to the v 2 input of A r , the s 2 output of C r (s 2Cr ) is coupled to the v 2 input of C i , and the s 2 output of C i (s 2Ci ) is coupled to the v 2 input of C r , so as to provide the overall function of: ##EQU16## wherein d 1Ar , d 1Ai , d 1Cr , d 1Ci ; d 2Ar , d 2Ai , d 2Cr , d 2Ci ; d 3Ar , d 3Ai , d 3Cr , d 3Ci ; t 1Ar , t 1Ai , t 1Cr , t 1Ci ; v 2Ar , v 2Ai , v 2Cr , v 2Ci ; t 2Ar , t 2Ai , t 2Cr , t 2Ci denote the serial data inputs (d 1 , d 2 , d 3 , t 1 , v 2 , t 2 ) of the subscripted arithmetic units (A r , A i , C r C i ); wherein c 1Ar , c 1Ai , c 1Cr , c 1Ci ; c 2Ar , c 2Ai , c 2Cr , c 2Ci ; c 3Ar , c 3Ai , c 3Cr , c 3Ci ; c 4Ar , c 4Ai , c 4Cr c 4Ci denote the sign control settings (c 1 , c 2 , c 3 , c 4 ) applied to the subscripted arithmetic units (A r , A i , C r , C i ), and z Ar , z Ai , z Cr , z Ci ) denote the (z) serial data outputs of the subscripted arithmetic units (A r , A i , C r , C i ) as a function of the inputs and control settings.

Claim 14

Apparatus as set forth in claim 9 comprisng two sets of four arithmetic units (A r , A i , C r , C i ) and (B r , B i , D r , D i ), the latter set being interconnected in the following manner: the s 1 output of B r (s 1Br ) is coupled to the d 3 input of D r , and the s 1 output of D r (s 1Dr ) is coupled to the d 3 input of B r , the s 1 output of B 1 (s 1Bi ) is coupled to the d 3 input of D i , and the s 1 output of D i (s 1Di ) is coupled to the d 3 input of B i , the s 2 output of B r (s 2Br ) is coupled to the v 2 input of B i , and the s 2 output of B i (s 2Bi ) is coupled to the v 2 input of B r , the s 2 output of D r (s 2Dr ) is coupled to the v 2 input of D i , and the s 2 output of D i (s 2Di ) is coupled to the v 2 input of D 4 , and the t 1 inputs of A r and A i ; B r and B i ; C r and C i ; and D r and D i are interconnected and designated respectively t 1A , t 1B , t 1C , t 1D ; and the t 2 inputs of A r and A i ; B r and B i ; C r and C i ; and D r and D i are interconnected and designated respectively t 2A , t 2B , t 2C , t 2D , so as to provide the overall function of: ##EQU17##

Claim 15

Apparatus as set forth in claim 10 for computation of the Fast Fourier Transform wherein the c constants are sign control settings assuming values of + or -1: t 1A , t 1B , t 1C , t 1D are respectively the cos 0, cosα, cos 2α, cos 3α, t 2A m t 2B , t 2C , t 2D are respectively the sin 0, sin α, sin 2α, sin 3α, so as to provide the overall function of: ##EQU18##

Claim 16

In a matrix processor for complex data, the combination comprising: a. a first serial input memory for real input data having a succession of evenly spaced taps for permuting the input data into an ideal shuffle, b. a second serial input memory for imaginary input data having a succession of evenly spaced taps for permuting the input data into an ideal shuffle, c. a plurality of vector adders each connected to at least two of said taps to produce real and imaginary, positive and negative outputs in accordance with the matrix ##EQU19## d. a like numbered plurality of vector multipliers, each multiplier in turn comprising a pair of multiplication means, each pair followed by summer with sign changing means, each multiplication means having one input connected to one output of a vector adder and another input connected to a serial source of complex data, said inputs to both multiplication means in a given vector multiplier being selected to provide either a real or an imaginary output, the outputs of said two multiplication means in a given vector multiplier being selected to provide either a real or an imaginary output, the outputs of said two multiplication means in each vector multiplier being combined to generate the real and imaginary elements of complex data, e. a real serial output memory for serially ordering the real processed data in accordance with the selected data information, and f. an imaginary serial output memory for serially ordering the imaginary processed data in accordance with the selected data permutation.

Claim 17

In a matrix processor for complex data, the combination comprising: a. a first serial input memory for real input data having a succession of evenly spaced taps for permuting the input data into an ideal shuffle, b. a second serial input memory for imaginary input data having a succession of evenly spaced taps for permuting the input data into an ideal shuffle, c. a plurality of vector adders each connected to at least two of said taps to produce real and imaginary, positive and negative outputs in accordance with the matrix ##EQU19## d. a like numbered plurality of vector multipliers, each multiplier in turn comprising a pair of multiplication means, each pair followed by summer with sign changing means, each multiplication means having one input connected to one output of a vector adder and another input connected to a serial source of complex data, said inputs to both multiplication means in a given vector multiplier being selected to provide either a real or an imaginary output, the outputs of said two multiplication means in a given vector multiplier being selected to provide either a real or an imaginary output, the outputs of said two multiplication means in each vector multiplier being combined to generate the real and imaginary elements of complex data, e. a real serial output memory for serially ordering the real processed data in accordance with the selected data information, and f. an imaginary serial output memory for serially ordering the imaginary processed data in accordance with the selected data permutation.

Claim 18

The combination set forth in claim 12 for computation of the Fast Fourier Transform wherein said second source of complex data is a pair of real and imaginary inputs corresponding to stored trigonometric weights equal to sine and cosine functions of angles selected in accordance with the number of resolution points in the transform.