Patent US4018990A successfully refreshed from Google Patents.
US4018990A
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Digital video synchronizer
Assignee: J CARL COOPER
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Filing: 1975-02-13
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Granted: 1977-04-19
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Expires: 1995-02-13
Abstract
Abstract A method and apparatus for synchronizing unrelated video type signals from two different sources without employing feedback loops between the two sources. Incoming video signals are converted from analog to digital form and are clocked into a shift register unit by input clock signals phase and frequency locked to the instantaneous horizontal frequency and the color burst frequency portions of the incoming signal. The digitized video signals progressing along the shift register are stored at the input clock signal rate in a random access (RAM) having a sufficient capacity to provide continuous output video signals during each field. The signals are clocked out from the RAM by output clock signals derived from the sync and color burst portions of a local signal comprising either composite video or composite color burst, which are synchronized with the local sync generator. The video signals fetched from the RAM are converted from digital to analog form by the output clock signals, are processed to include standard sync, blanking and color burst signals, and are coupled to follow-on equipment. The sync burst portions of the incoming non-synchronized video signals are deleted during storage in the shift register so that a smaller shift register can store an entire video field. The shift register has a plurality of output taps providing different coarse delay periods only one of which is enabled by a vertical sync pulse in the output clock train prior to transfer of a given field into the RAM.
Inventors
- 👤 Ronald D. Long
- 👤 Allan L. Swain
- 👤 Thomas C. Lyon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:08
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/0736; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
119 words
The method for synchronizing first and second input video type signals each of which comprises horizontal sync portions, said method comprising: a. successively sampling said first video input signal at a first clock rate derived from said first video input signal; b. storing the signals sampled in step (a) in a memory; c. delaying said signals in said memory for a predetermined delay interval determined by the difference in phase between predetermined portions of said first video input signal and said second video input signal; d. reading the signals stored in said memory at a second clock rate synchronously related to said second video input signal; and e. periodically changing said predetermined delay interval when said phase difference varies.
Claim 2
Independent Claim
119 words
The method for synchronizing first and second input video type signals each of which comprises horizontal sync portions, said method comprising: a. successively sampling said first video input signal at a first clock rate derived from said first video input signal; b. storing the signals sampled in step (a) in a memory; c. delaying said signals in said memory for a predetermined delay interval determined by the difference in phase between predetermined portions of said first video input signal and said second video input signal; d. reading the signals stored in said memory at a second clock rate synchronously related to said second video input signal; and e. periodically changing said predetermined delay interval when said phase difference varies.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein said step (a) of sampling includes the step of converting said first video input signal from analog-to-digital form.
Claim 4
Dependent Claim
24 words
The method of claim 1 wherein said first clock rate is synchronously related to the horizontal sync portion of said first input video signal.
Claim 5
Dependent Claim
35 words
The method of claim 3 wherein said input video signals further include color burst portions and said first clock rate is also synchronously related to the color burst portion of said first input video signal.
Claim 6
Dependent Claim
36 words
The method of claim 1 wherein said step (c) of delaying includes the step of (i) clocking said storage signals along a shift register having a plurality of taps each providing a different fixed delay period.
Claim 7
Dependent Claim
35 words
The method of claim 5 wherein said step of delaying further includes the step (ii) of storing the signals output from one of said taps in a random access memory at said first clocking rate.
Claim 8
Dependent Claim
24 words
The method of claim 1 wherein said second clock rate is synchronously related to the horizontal sync portions of said second input video signal.
Claim 9
Dependent Claim
35 words
The method of claim 7 wherein said input video signals further include color burst portions and said second clock rate is also synchronously related to the color burst portions of said second input video signal.
Claim 10
Dependent Claim
23 words
The method of claim 1 wherein said step (e) is performed at the beginning of a field in said first video input signal.
Claim 11
Dependent Claim
148 words
A video synchronizer system for synchronizing first and second input video signals each of which comprises horizontal sync portions, said system comprising: means for successively sampling said first video input signal at a first clock rate derived from said first video input signal; memory means coupled to said sampling means for storing the signals sampled in said sampling means; means coupled to said memory means for delaying said signals stored in said memory means for a predetermined delay interval determined by the difference in phase between predetermined portions of said first video input signal and said second video input signal; means coupled to said memory means for reading the signal stored in said memory means at a second clock rate synchronously related to said second video input signals; and timing means coupled to said memory means for periodically changing said predetermined delay interval when said phase difference varies.
Claim 12
Dependent Claim
148 words
A video synchronizer system for synchronizing first and second input video signals each of which comprises horizontal sync portions, said system comprising: means for successively sampling said first video input signal at a first clock rate derived from said first video input signal; memory means coupled to said sampling means for storing the signals sampled in said sampling means; means coupled to said memory means for delaying said signals stored in said memory means for a predetermined delay interval determined by the difference in phase between predetermined portions of said first video input signal and said second video input signal; means coupled to said memory means for reading the signal stored in said memory means at a second clock rate synchronously related to said second video input signals; and timing means coupled to said memory means for periodically changing said predetermined delay interval when said phase difference varies.
Claim 13
Dependent Claim
26 words
The combination of claim 10 wherein said sampling means includes an analog-to-digital converter means for generating successive multibit digital characters from said first input video signals.
Claim 14
Dependent Claim
24 words
The combination of claim 10 wherein said first clock rate is synchronously related to the horizontal sync portions of said first input video signal.
Claim 15
Dependent Claim
35 words
The combination of claim 12 wherein said input video signals further include color burst portions and said first clock rate is also synchronously related to the color burst portions of said first input video signal.
Claim 16
Dependent Claim
42 words
The combination of claim 10 wherein said memory means includes a shift register having a plurality of output taps each providing a different fixed delay period, and wherein said timing means includes means for selecting one of said plurality of output taps.
Claim 17
Dependent Claim
26 words
The combination of claim 14 wherein said memory means further includes a random access memory having a data input coupled to one of said output taps.
Claim 18
Dependent Claim
23 words
The combination of claim 10 wherein said second clock rate is synchronously related to the horizontal sync portions of said second video signal.
Claim 19
Dependent Claim
35 words
Th combination of claim 16 wherein said input video signals further include color burst portions and said second clock rate is also synchronously related to the color burst portions of said second input video signal.
Claim 20
Dependent Claim
32 words
The combination of claim 10 wherein said timing means includes means for changing said predetermined delay interval at the beginning of a field of video information in said first input video signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-18 | 1980-10-18 | 1981-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-18 | 1984-10-18 | 1985-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-18 | 1988-10-18 | 1989-04-19 | $7700.00 | Window Closed / Lapsed |