Patent US4017849A successfully refreshed from Google Patents.
US4017849A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for analog to digital conversion
Assignee: AT&T Inc
•
Filing: 1975-08-28
•
Granted: 1977-04-12
•
Expires: 1995-08-28
Abstract
Abstract An input analog signal is converted to a digital output signal by an oversampled predictive DPCM coder which includes an n stage delay line in the feedback loop. The n delay line outputs are weighted by coefficients a i . . . a n selected according to the relationship ##EQU1## AND THEN SUMMED. Alternatively, the feedback loop may comprise a chain of n integrators arranged so that the signal fed back to the comparator is the sum of single, double, triple . . . n order integration. By so doing, the coder attenuates the signal power at the quantizer input while the attenuator coefficients are independent of the input signal statistics. A similar technique may also be applied in an oversampled error feedback coder, which includes a feedback loop having an n stage delay line. Here again, the delay line outputs are weighted in accordance with the above relationship. Alternatively, a chain of n integrators may be used in the coder input, and an identical chain employed in the feedback loop. By so doing, the coder attenuates the coding noise power in the signal band while the coder design is rendered independent of the quantizing error statistics.
Inventors
- 👤 Stuart Keene Tewksbury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:24
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/04; G; G06; G06T; G06T9/00; G06T9/004
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
142 words
A differential pulse code modulation encoder for converting an analog input signal to a digital output signal, said output signal representing the difference between said input signal and a decoded version of said output signal, comprising a comparator for generating an error signal formed by subtracting said decoded version of said output signal from said input signal, quantizing means substantially instantaneously responsive to said comparator for generating said digital output signal by sampling said error signal and converting said samples to digital form, and means for generating said decoded version of said output signal characterized by a digital to analog converter for generating an intermediate analog signal in response to said digital output signal, a serial chain of at least three integrators for receiving said intermediate analog signal, and means for summing the outputs of each of said integrators of said chain.
Claim 2
Dependent Claim
142 words
A differential pulse code modulation encoder for converting an analog input signal to a digital output signal, said output signal representing the difference between said input signal and a decoded version of said output signal, comprising a comparator for generating an error signal formed by subtracting said decoded version of said output signal from said input signal, quantizing means substantially instantaneously responsive to said comparator for generating said digital output signal by sampling said error signal and converting said samples to digital form, and means for generating said decoded version of said output signal characterized by a digital to analog converter for generating an intermediate analog signal in response to said digital output signal, a serial chain of at least three integrators for receiving said intermediate analog signal, and means for summing the outputs of each of said integrators of said chain.
Claim 3
Dependent Claim
34 words
The invention defined in claim 1 wherein said analog input signal has a bandwidth f.sub. o and said quantizing means is arranged for sampling at a rate of at least 5 f o .
Claim 4
Dependent Claim
16 words
The invention defined in claim 1 wherein said digital output signal includes a plurality of bits.
Claim 5
Dependent Claim
45 words
In a differential pulse code modulation encoder including means for substantially instantaneously converting an analog input signal into a digital output signal which represents said input signal, a decoder for reconverting said output signal to a good prediction of said input signal, said decoder comprising
Claim 6
Dependent Claim
45 words
In a differential pulse code modulation encoder including means for substantially instantaneously converting an analog input signal into a digital output signal which represents said input signal, a decoder for reconverting said output signal to a good prediction of said input signal, said decoder comprising
Claim 7
Dependent Claim
42 words
first means including a serial chain of M integrators, wherein M ≧ 3, for receiving said output signal, and 2. second means for obtaining the sum of the outputs of each of said integrators of said chain to form said good prediction.
Claim 8
Dependent Claim
42 words
first means including a serial chain of M integrators, wherein M ≧ 3, for receiving said output signal, and 2. second means for obtaining the sum of the outputs of each of said integrators of said chain to form said good prediction.
Claim 9
Dependent Claim
31 words
The invention defined in claim 4 wherein said first means further includes means for converting said received output signal to an analog signal and wherein said M integrators are analog integrators.
Claim 10
Dependent Claim
40 words
The invention defined in claim 5 wherein said analog signal has a bandwidth f.sub. o and said converting means includes a quantizer adapted to sample said analog signal at a rate at least five times greater than f o .
Claim 11
Dependent Claim
16 words
The invention defined in claim 4 wherein said digital output signal includes a plurality of bits.
References Cited (Backward Citations)
US2916553A
Cited
US3305854A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-11 | 1980-10-11 | 1981-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-11 | 1984-10-11 | 1985-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-11 | 1988-10-11 | 1989-04-12 | $7700.00 | Window Closed / Lapsed |