Synchro-to-digital converter

Claim 1

A synchro-to-digital signal converter comprising, in combination, a polyphase-synchro signal converter connected to a synchro system to receive synchro signals therefrom, and including operational circuits each comprising an operational amplifier, first and second resistors connected in the input side of said operational amplifier, and a third resistor provided in a feedback circuit of said operational amplifier, whereby, upon reception of an output signal from a synchro rotor corresponding to an input rotational angle θ thereof, said operational circuits provide 2 n electrical output signals where n is an integer greater than zero, having a phase angle α for the input rotational angle θ in the form of E.sub.m K sin (θ+(α) where E m is a maximum value of a voltage ##EQU5##thereby to obtain output signals corresponding to an 2 n phase synchro; a phase selector connected to the output of said synchro signal converter and operable to supply two selected adjacent output phase signals; a single D-A converter connected to the output of said phase selector and receiving said two selected phase signals therefrom, and driven by pure binary coded signals; and an operational device, connected to said D-A converter, having a reference pulse generator for generating timing pulses synchronized with a half period of a carrier for the synchro system and operable to initiate operation of said operational device and also to generate a train of polarity discriminating pulses, a polarity sensor connected to said reference pulse generator and to said D-A converter for discriminating polarity of an output signal from said D-A converter, an oscillator generating clock pulses, a pulse distributor connected to said oscillator, flip-flop and gate circuits connected to said pulse distributor, and a clock pulse control circuit connected between said oscillator and said pulse distributor for controlling the introduction of said clock pulses to said pulse distributor and said flip-flop and gate circuits, whereby the operation of said operational device is initiated upon generation of said timing pulses, with all of the flip-flops outputs from said flip-flop and gate circuits being set to "0" upon reception of a first allocating pulse from said pulse generator, and the subsequent delivery of a second allocating pulse ad succeeding allocating pulses from said pulse distributor temporarily setting the flip-flop outputs, from the higher bit to the lower bit, to "1" through the flip-flop and gate circuits, the "1" state of the flip-flop outputs being maintained or converted to "0" depending on a polarity signal simultaneously delivered to said flip-flop and gate circuits from the said polarity sensor, thereby to carry out operation up to the least significant bit, and, when the operation up to the least significant bit is completed, delivering an operation completion signal; said operational device being connected to said phase selector to supply the higher bit signals thereto to select said two adjacent phase signals from said polyphase-synchro signal converter for supply to said single D-A converter; said operational device being connected to said D-A converter to supply the lower bit signals thereto for driving said D-A converter to convert the rotational angle of a synchro input shaft into a value expressed in a pure binary code.