Patent US606525A successfully refreshed from Google Patents.
Patent US4017750A successfully refreshed from Google Patents.
US4017750A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for effectively making integrated impedances accurate
Assignee: US Philips Corp
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Filing: 1976-04-08
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Granted: 1977-04-12
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Expires: 1996-04-08
Abstract
Abstract A circuit arrangement for effectively correcting the absolute values of a plurality of impedances when they already have impedance values in the correct ratio to each other. Current going through each impedance is multiplied by a ratio derived from a precision impedance. The circuit is particularly useful in integrated circuit technology where impedance ratios can be accurately controlled but not so readily the absolute values of the impedances.
Inventors
- 👤 Johannes Otto Voorman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:46
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/46; G; G01; G01R; G01R27/00; G01R27/02; G01R27/16; G01R31/00; G01R31/28; G01R31/316; G06; G06G; G06G7/00; G06G7/12; G06G7/16; H03H11/02; H03H11/40; H03H11/42
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
A circuit arrangement, comprising: a first impedance; a plurality of second impedances, said first and plurality of second impedances having accurately predetermined impedance ratios with respect to each other but inaccurately determined absolute impedance values; means for electrically connecting one end of said first impedance to a source of constant potential; a precision impedance electrically connected at one end thereof to said one end of said first impedance; a current divider circuit electrically connected between the other end of said first impedance and the other end of said precision impedance for producing first and second output currents having the same ratio as the impedance ratio between said first impedance and said precision impedance; a separate current multiplier circuit corresponding to and electrically connected to each one of said plurality of second impedances, each of said current multiplier circuits being responsive to current flowing through the corresponding electrically connected second impedance and being responsive to said first and second output currents of said current divider circuit for producing a current multiplier output current proportional to the product of said current flowing through the corresponding electrically connected second impedance and the ratio between said first and second output currents of said current divider circuit, whereby the values of said current multiplier output currents are accurately determined by said accurately predetermined impedance ratios and the impedance value of said precision impedance and are not substantially affected by the absolute impedance values of said first and plurality of second impedances.
Claim 2
Dependent Claim
246 words
A circuit arrangement, comprising: a first impedance; a plurality of second impedances, said first and plurality of second impedances having accurately predetermined impedance ratios with respect to each other but inaccurately determined absolute impedance values; means for electrically connecting one end of said first impedance to a source of constant potential; a precision impedance electrically connected at one end thereof to said one end of said first impedance; a current divider circuit electrically connected between the other end of said first impedance and the other end of said precision impedance for producing first and second output currents having the same ratio as the impedance ratio between said first impedance and said precision impedance; a separate current multiplier circuit corresponding to and electrically connected to each one of said plurality of second impedances, each of said current multiplier circuits being responsive to current flowing through the corresponding electrically connected second impedance and being responsive to said first and second output currents of said current divider circuit for producing a current multiplier output current proportional to the product of said current flowing through the corresponding electrically connected second impedance and the ratio between said first and second output currents of said current divider circuit, whereby the values of said current multiplier output currents are accurately determined by said accurately predetermined impedance ratios and the impedance value of said precision impedance and are not substantially affected by the absolute impedance values of said first and plurality of second impedances.
Claim 3
Dependent Claim
122 words
A circuit arrangement as defined in claim 1 wherein said current divider circuit comprises first, second, third and fourth transistors, the emitters of said first and second transistors being electrically interconnected, the emitters of said third and fourth transistors being electrically interconnected, the bases of said first and fourth transistors being electrically interconnected, the bases of said second and third transistors being electrically interconnected, said other end of said precision impedance being electrically connected to said interconnected bases of said first and fourth transistors, said other end of said first impedance being electrically connected to said interconnected bases of said second and third transistors, and the collector currents of said third and fourth transistors being respectively said second and first output currents.
Claim 4
Dependent Claim
51 words
A circuit arrangement as defined in claim 2 and further comprising a first diode electrically connecting said interconnected emitters of said first and second transistors to a point of constant potential, and a resistance electrically connecting said interconnected emitters of said third and fourth transistors to said point of constant potential.
Claim 5
Dependent Claim
96 words
A circuit arrangement as defined in claim 3 further comprising second and third diodes respectively electrically connecting the collectors of said third and fourth transistors to said one end of said first impedance, a first plurality of transistors equal in number to said current multiplier circuits, the base-emitter junctions of said first plurality of transistors being electrically connected in parallel with said second diode, and a second plurality of transistors equal in number to said current multiplier circuits, the base-emitter junctions of said second plurality of transistors being electrically connected in parallel with said third diode.
Claim 6
Dependent Claim
141 words
A circuit arrangement as defined in claim 4 wherein each of said current multiplier circuits comprises fifth, sixth, seventh and eighth transistors, the emitters of said fifth and sixth transistors being electrically interconnected, the emitters of said seventh and eighth transistors being electrically interconnected, the bases of said fifth and eighth transistors being electrically interconnected, the bases of said sixth and seventh transistors being electrically interconnected, the collector of said sixth transistor being electrically connected to a collector of one of the transistors of said first plurality of transistors, the collector of said seventh transistor being electrically connected to a collector of one of the transistors of said second plurality of transistors, the collector of said fifth transistor being connected to the corresponding electrically connected second impedance, and the collector current of said eighth transistor being said current multiplier output current.
Claim 7
Dependent Claim
74 words
A circuit arrangement as defined in claim 5 and further comprising a fourth diode electrically connecting said interconnected emitters of said fifth and sixth transistors to said point of constant potential, an auxiliary transistor having a collector-emitter path electrically connecting the interconnected emitters of said seventh and eighth transistors to said point of constant potential, and a fifth diode electrically connecting the base of said auxiliary transistor to the collector of said seventh transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-11 | 1980-10-11 | 1981-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-11 | 1984-10-11 | 1985-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-11 | 1988-10-11 | 1989-04-12 | $7700.00 | Window Closed / Lapsed |