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Patent US4017740A successfully refreshed from Google Patents.
US4017740A
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Synchronization of digital circuits by bus triggering
Assignee: HP Inc
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Filing: 1975-04-30
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Granted: 1977-04-12
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Expires: 1995-04-30
Abstract
Abstract Data flow between multiple digital circuits having various internal clock rates is controlled by an asynchronous trigger bus. A trigger pulse is generated on the trigger bus when a trigger condition is simultaneously detected in two circuits desiring to communicate.
Inventors
- 👤 William A. Farnbach
- 👤 Charles T. Small
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:34
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
164 words
A method for synchronizing the simultaneous interrogation of a plurality of digital circuits, said method comprising the steps of: detecting a first logical state within a first digital circuit; said first digital circuit being responsive to first clock signals; detecting a second logical state within a second digital circuit; said second digital circuit operating asynchronously with respect to said first digital circuit and not being responsive to said first clock signals nor to phase or harmonically related components derived therefrom; providing a first logic level to an electrical signal line in response to the detection of said first logic state; providing a first logic level to said electrical signal line in response to the detection of said second logic state; inhibiting the production of said first logic level and providing a second logic level to said electrical signal line if said first and second logic states are not detected simultaneously; and generating one or more enable signals in response to said first logic level.
Claim 2
Independent Claim
164 words
A method for synchronizing the simultaneous interrogation of a plurality of digital circuits, said method comprising the steps of: detecting a first logical state within a first digital circuit; said first digital circuit being responsive to first clock signals; detecting a second logical state within a second digital circuit; said second digital circuit operating asynchronously with respect to said first digital circuit and not being responsive to said first clock signals nor to phase or harmonically related components derived therefrom; providing a first logic level to an electrical signal line in response to the detection of said first logic state; providing a first logic level to said electrical signal line in response to the detection of said second logic state; inhibiting the production of said first logic level and providing a second logic level to said electrical signal line if said first and second logic states are not detected simultaneously; and generating one or more enable signals in response to said first logic level.
Claim 3
Dependent Claim
32 words
The method as in claim 1, wherein the step of detecting the first logical state includes the step of recognizing a first selected pattern of logical events within the first digital circuit.
Claim 4
Dependent Claim
32 words
The method as in claim 2, wherein the step of detecting a second logical state includes the step of recognizing a second selected pattern of logical events within a second digital circuit.
Claim 5
Dependent Claim
31 words
The method as in claim 3, wherein the step of detecting a first logical state includes the step of generating a first control signal when the first logical state is detected.
Claim 6
Dependent Claim
30 words
The method of claim 4, wherein the step of detecting a second logical state includes the step of generating a second control signal when the second logical state is detected.
Claim 7
Dependent Claim
44 words
The method as in claim 5, wherein the step of generating one or more enable signals includes the step of generating a first enable signal in the first digital circuit and the step of generating a second enable signal in the second digital circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-11 | 1980-10-11 | 1981-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-11 | 1984-10-11 | 1985-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-11 | 1988-10-11 | 1989-04-12 | $7700.00 | Window Closed / Lapsed |