Patent US4016596A successfully refreshed from Google Patents.
US4016596A
Expired / Lapsed
US
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High performance integrated bipolar and complementary field effect transistors
Assignee: International Business Machines Corp
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Filing: 1976-01-26
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Granted: 1977-04-05
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Expires: 1996-01-26
Abstract
Abstract A method for fabricating both bipolar as well as complementary MOS field effect transistors, i.e., BI-CMOS transistors in the same semiconductor substrate. The preferred embodiment of the method provides bipolar and CMOS transistors having breakdown voltages (BV ceo ) in excess of 10 volts and CMOS devices having no latchup problems, with a minimum number of processing steps. The method also contemplates the formation of auxiliary devices such as resistors and Schottky Barrier diodes.
Inventors
- 👤 Ingrid Emese Magdo
- 👤 Steven Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/40; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10W; H10W10/00; H10W10/01
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
234 words
A semiconductor integrated circuit comprising: a monocrystalline semiconductor substrate of a first conductivity type; a first monocrystalline layer of a second conductivity type disposed over said substrate; a subcollector region of said second conductivity type extending from said substrate into said first layer and below the upper surface thereof; second and third regions of said first conductivity type extending from said substrate to the upper surface of said first layer, said scond region surrounding said subcollector region, the conductivity level of said second region being greater than that of said third region; a dielectric layer disposed over said first monocrystalline layer having openings therein over said subcollector region, said third region and at another location over said first monocrystalline layer; a second layer disposed over said dielectric layer and in said openings; said second layer including monocrystalline regions over the portions of said first monocrystalline layer exposed by said openings, polycrystalline regions over said dielectric layer in areas contiguous to each said monocrystalline region, and dielectric isolation regions separating each said contiguous polycrystalline/monocrystalline regions from every other contiguous polycrystalline/monocrystalline region; a bipolar transistor of said second conductivity type formed in said monocrystalline region over said subcollector; field effect transistors of second and first channel types formed in said monocrystalline regions over said third region and said another location, respectively; and a polycrystalline silicon resistor formed in a polycrystalline region disposed over said dielectric layer.
Claim 2
Dependent Claim
234 words
A semiconductor integrated circuit comprising: a monocrystalline semiconductor substrate of a first conductivity type; a first monocrystalline layer of a second conductivity type disposed over said substrate; a subcollector region of said second conductivity type extending from said substrate into said first layer and below the upper surface thereof; second and third regions of said first conductivity type extending from said substrate to the upper surface of said first layer, said scond region surrounding said subcollector region, the conductivity level of said second region being greater than that of said third region; a dielectric layer disposed over said first monocrystalline layer having openings therein over said subcollector region, said third region and at another location over said first monocrystalline layer; a second layer disposed over said dielectric layer and in said openings; said second layer including monocrystalline regions over the portions of said first monocrystalline layer exposed by said openings, polycrystalline regions over said dielectric layer in areas contiguous to each said monocrystalline region, and dielectric isolation regions separating each said contiguous polycrystalline/monocrystalline regions from every other contiguous polycrystalline/monocrystalline region; a bipolar transistor of said second conductivity type formed in said monocrystalline region over said subcollector; field effect transistors of second and first channel types formed in said monocrystalline regions over said third region and said another location, respectively; and a polycrystalline silicon resistor formed in a polycrystalline region disposed over said dielectric layer.
Claim 3
Dependent Claim
21 words
An integrated circuit as in claim 1 wherein said polycrystalline region containing said resistor is dielectrically isolated from said monocrystalline regions.
Claim 4
Dependent Claim
33 words
An integrated circuit as in claim 2 wherein said resistor is of a first conductivity type and is located in said polycrystalline region which is contiguous to the base of said bipolar transistor.
Claim 5
Dependent Claim
66 words
An integrated circuit as in claim 1 further comprising; a reach-through region of a second conductivity type formed in said second layer and connected to said subcollector region through an opening in said dielectric layer; said reach-through region including a polycrystalline silicon region contiguous thereto; wherein said polycrystalline resistor is of said second conductivity type and is located in said region contiguous to said reach-through region.
Claim 6
Dependent Claim
245 words
A semiconductor integrated circuit comprising: a monocrystalline semiconductor substrate of a first conductivity type; a first monocrystalline layer of a second conductivity type disposed over said substrate; a subcollector region of said second conductivity type extending from said substrate into said first layer and below the upper surface thereof; second and third regions of said first conductivity type extending from said substrate to the upper surface of said first layer, said second region surrounding said subcollector region, the conductivity level of said second region being greater than that of said third region; a dielectric layer disposed over said first monocrystalline layer having openings therein over said subcollector region, said third region and at another location over said first monocrystalline layer; a second layer disposed over said dielectric layer and in said openings; said second layer including monocrystalline regions over the portion of said first monocrystalline layer exposed by said openings, polycrystalline regions on the surface of said dielectric layer in areas contiguous to each said monocrystalline region, and dielectric isolation regions separating each said contiguous polycrystalline/monocrystalline regions from every other contiguous polycrystalline/monocrystalline region; field effect transistors of second and first channel types formed in said monocrystalline regions over said third region and said another location, respectively; a bipolar transistor of said second conductivity type formed in said contiguous polycrystalline/monocrystalline region over said subcollector; said bipolar transistor including emitter and intrinsic base regions in said monocrystalline region and an extrinsic base region in said polycrystalline region;
Claim 7
Dependent Claim
245 words
A semiconductor integrated circuit comprising: a monocrystalline semiconductor substrate of a first conductivity type; a first monocrystalline layer of a second conductivity type disposed over said substrate; a subcollector region of said second conductivity type extending from said substrate into said first layer and below the upper surface thereof; second and third regions of said first conductivity type extending from said substrate to the upper surface of said first layer, said second region surrounding said subcollector region, the conductivity level of said second region being greater than that of said third region; a dielectric layer disposed over said first monocrystalline layer having openings therein over said subcollector region, said third region and at another location over said first monocrystalline layer; a second layer disposed over said dielectric layer and in said openings; said second layer including monocrystalline regions over the portion of said first monocrystalline layer exposed by said openings, polycrystalline regions on the surface of said dielectric layer in areas contiguous to each said monocrystalline region, and dielectric isolation regions separating each said contiguous polycrystalline/monocrystalline regions from every other contiguous polycrystalline/monocrystalline region; field effect transistors of second and first channel types formed in said monocrystalline regions over said third region and said another location, respectively; a bipolar transistor of said second conductivity type formed in said contiguous polycrystalline/monocrystalline region over said subcollector; said bipolar transistor including emitter and intrinsic base regions in said monocrystalline region and an extrinsic base region in said polycrystalline region;
Claim 8
Dependent Claim
15 words
at least a portion of said extrinsic base region being located over said second region.
Claim 9
Dependent Claim
15 words
at least a portion of said extrinsic base region being located over said second region.
Claim 10
Dependent Claim
19 words
A semiconductor integrated circuit as in claim 5 and further comprising a resistor located in said extrinsic base region.
Claim 11
Dependent Claim
51 words
An integrated circuit as in claim 1 wherein the concentration level of said second region is at least 5 × 10 17 atoms per cm 3 and of said third region is between 4 × 10 16 and 10 17 atoms per cm 3 at the surface of said monocrystalline layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |