CCD range-doppler processor

Claim 2

Doppler range processing apparatus including means for premultiplying time sampled radar signal returns to provide up-chirp multiplication of said time sampled signals; charge transfer device shift register means having N storage bits for storing respective up-chirp weighted samples of said radar return signals occuring during a pulse repetition interval; for each bit of said shift register means, first and second charge transfer device chirp Z-transform filters; transfer means for transferring signals stored in the bits of said shift register as inputs to the respective first and second chirp filters for each respective bit; said first chirp filters being adapted to provide in-phase weighting of said input signals thereto; said second chirp filters being adapted to provide quadrature-phase weighting of said input signals thereto; means connecting said filter outputs to means for summing and squaring weighted signal outputs from said filters.

Claim 3

Apparatus according to claim 1, wherein said charge transfer device shift register means and said chirp filters are all incorporated into a single semiconductor substrate.

Claim 4

Apparatus according to claim 1, wherein said premultiplication means is adapted to weight said time-sampled signal returns according to a function e i .sup.πn.spsp.2/N where n is an integer representing the n th sampled signal return and N is the total number of sampled signal returns.

Claim 5

Apparatus according to claim 1, wherein said premultiplication means is adapted to weight said time-sampled signal returns according to a function W n e i .sup.πn.spsp.2/N, where W n is a weighting factor dependent on n; n is an integer representing the n th sampled signal return, and N is the total number of sampled signal returns.

Claim 6

Apparatus according to claim 1, wherein said premultiplication means is adapted to weight said time sampled signal returns with an amplitude modulated weighting signal.

Claim 7

Doppler radar processing apparatus including: means for premultiplying time sampled radar signal returns to provide up-chirp multiplication of said time sampled signals and producing first and second pre-weighted signal sample outputs, said first outputs corresponding with in-phase signal components and said second outputs corresponding with quadrature-phase signal components; first charge transfer device shift register means connected to receive said second weighted signal outputs from said pre-weighting means; for each bit of said first and second shift register means individual first and second charge transfer device chirp correlation filter means; means for transferring signals stored in the bits of said first shift register means to the first and second chirp correlation filter means for each respective bit of said first shift register means; means for transferring signals stored in the bits of said second shift register means to the first and second chirp correlation filter means for each respective bit of said second shift register means; said first chirp correlation filter means adapted to weight input signals thereto with an in-phase weighting factor; said second chirp correlation filter means adapted to weight input signals thereto according to a quadrature-phase weighting coefficient; first means for summing and squaring the outputs from the first chirp correlation filters of said first shift register means and of said second chirp correlation filter outputs of said second shift register means; second means for summing and squaring the outputs from the first chirp correlation filter means of said second shift register means and of the second chirp correlation filter outputs of said first shift register means.

Claim 8

Doppler radar processing apparatus including: means for premultiplying time sampled radar signal returns to provide up-chirp multiplication of said time sampled signals and producing first and second pre-weighted signal sample outputs, said first outputs corresponding with in-phase signal components and said second outputs corresponding with quadrature-phase signal components; first charge transfer device shift register means connected to receive said second weighted signal outputs from said pre-weighting means; for each bit of said first and second shift register means individual first and second charge transfer device chirp correlation filter means; means for transferring signals stored in the bits of said first shift register means to the first and second chirp correlation filter means for each respective bit of said first shift register means; means for transferring signals stored in the bits of said second shift register means to the first and second chirp correlation filter means for each respective bit of said second shift register means; said first chirp correlation filter means adapted to weight input signals thereto with an in-phase weighting factor; said second chirp correlation filter means adapted to weight input signals thereto according to a quadrature-phase weighting coefficient; first means for summing and squaring the outputs from the first chirp correlation filters of said first shift register means and of said second chirp correlation filter outputs of said second shift register means; second means for summing and squaring the outputs from the first chirp correlation filter means of said second shift register means and of the second chirp correlation filter outputs of said first shift register means.

Claim 9

Apparatus according to claim 6, further including means for summing the outputs of said first and second summing and squaring means.

Claim 10

Apparatus according to claim 7, wherein said first and second shift register means together with said first and second charge transfer device chirp correlation filter means all are provided on a common semiconductor substrate.

Claim 11

Apparatus according to claim 8, wherein said charge transfer device shift register means and said charge transfer device chirp correlation filter means all comprise charge coupled devices.

Claim 12

Apparatus according to claim 6, further including for each said chirp correlation filter means, differential current integration means for receiving outputs from said filter menas; and means for sampling and temporarily storing the output from said differential current integration means.

Claim 13

Apparatus according to claim 6, wherein said pre-weighting means includes first signal mixer means for receiving radar return video signals and a reference signal, and for providing time sampled outputs from said first mixing means; second signal mixing means for receiving said radar return video signals and said reference signals phase-shifted by 90°, and for producing time-sampled outputs from said second mixer means; third signal means connected for receiving said time sampled outputs from said first mixing means and an in-phase up-chirp weighting signal; fourth signal mixing means for receiving time-sampled outputs from said second mixer means and a quadrature-phase up-chirp weighting signal; fifth signal mixing means for receiving said time-sampled outputs from said first mixing means and a quadrature-phase up-chirp weighting signal; sixth signal mixing means for receiving said time-sampled outputs from said second signal mixing means and an in-phase up-chirp weighting signal; difference amplifier means connected to receive outputs from said third and fourth signal mixing means; summation amplifier means connected to receive inputs from said fifth and sixth signal mixing means; means connecting said difference amplifier output to apply inputs to said first shift register means and means connecting said summation amplifier output to apply inputs to said second shift register means.

Claim 14

Apparatus according to claim 11, wherein said up-chirp weighting signals have a constant amplitude.

Claim 15

Apparatus according to claim 11, wherein said up-chirp weighting signals are amplitude modulated to provide apodization of the weighted signals.