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Patent US4016430A successfully refreshed from Google Patents.
US4016430A
Expired / Lapsed
US
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MIS logical circuit
Assignee: Hitachi Ltd
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Filing: 1975-12-23
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Granted: 1977-04-05
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Expires: 1995-12-23
Abstract
Abstract In a logical circuit comprising a load and a driving MISFET, a depletion type MISFET is connected between the load and the driving MISFET and a voltage which has a smaller absolute value than the absolute value of the difference between a supply voltage and a threshold voltage of the depletion type MISFET is impressed on the gate electrode of the depletion type MISFET.
Inventors
- 👤 Tadao Kanezuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
131 words
A logical circuit comprising: a logic block including at least one input terminal and an output terminal, and at least one driving insulated gate field effect transistor connected between a respective input terminal and the output terminal of said logic block; and a depletion type insulated gate field effect transistor and a load element connected in series between a load supply voltage terminal to which a supply voltage is applied and the output of said logic block; and wherein the gate electrode of said depletion type insulated gate field effect transistor is applied with a voltage the absolute value of which is less than the difference between the absolute value of said supply voltage and the absolute value of the threshold voltage of said depletion type insulated gate field effect transistor.
Claim 2
Dependent Claim
131 words
A logical circuit comprising: a logic block including at least one input terminal and an output terminal, and at least one driving insulated gate field effect transistor connected between a respective input terminal and the output terminal of said logic block; and a depletion type insulated gate field effect transistor and a load element connected in series between a load supply voltage terminal to which a supply voltage is applied and the output of said logic block; and wherein the gate electrode of said depletion type insulated gate field effect transistor is applied with a voltage the absolute value of which is less than the difference between the absolute value of said supply voltage and the absolute value of the threshold voltage of said depletion type insulated gate field effect transistor.
Claim 3
Dependent Claim
33 words
A logical circuit according to claim 1, wherein said load element comprises an insulated gate field effect transistor the gate of which is coupled to a clock pulse terminal for receiving clock pulses.
Claim 4
Dependent Claim
20 words
A logical circuit according to claim 1, wherein the gate of said depletion type transistor is connected to ground potential.
Claim 5
Dependent Claim
33 words
A logical circuit according to claim 3, wherein said load element comprises an insulated gate field effect transistor the gate of which is coupled to a clock pulse terminal for receiving clock pulses.
References Cited (Backward Citations)
US3818245A
Cited
US3944848A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |