Patent US4015252A successfully refreshed from Google Patents.
US4015252A
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High speed serial data synchronization scheme
Assignee: United States Department of the Navy
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Filing: 1975-06-25
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Granted: 1977-03-29
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Expires: 1995-06-25
Abstract
Abstract A serial-to-parallel data conversion and synchronization scheme in which alurality of active logic elements are utilized as delay lines. Each of the delay lines introduces a delay equal to the period of one data bit and one additional delay line introduces a delay equal to one half the period of a data bit. The input of the first delay line is connected to the data input of a first flip-flop and the outputs of each of the plurality of delay lines are each connected to the data input of a flip-flop. The output of the additional delay line is connected to the clock inputs of each of the flip-flops whereby the serial data word is converted to a parallel data word and the conversion is internally clocked by the delay lines themselves.
Inventors
- 👤 Jerome J. Symanski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:38
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; H; H03; H03M; H03M9/00; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/45
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
124 words
A device for synchronizing and converting a serial data bit stream to a parallel data format comprising: a serially connected plurality of strings of active logic devices, each said string of active logic devices introducing a delay equal to the period of one said data bit: one additional string of active logic devices having an input serially connected to said plurality of strings and an output, introducing a delay less than the period of one said data bit; a plurality of flip-flops each having data and clock inputs and an output, each data input being connected to one end of one of said plurality of strings of active logic devices and each clock input being connected to said output of said one additional string.
Claim 2
Independent Claim
124 words
A device for synchronizing and converting a serial data bit stream to a parallel data format comprising: a serially connected plurality of strings of active logic devices, each said string of active logic devices introducing a delay equal to the period of one said data bit: one additional string of active logic devices having an input serially connected to said plurality of strings and an output, introducing a delay less than the period of one said data bit; a plurality of flip-flops each having data and clock inputs and an output, each data input being connected to one end of one of said plurality of strings of active logic devices and each clock input being connected to said output of said one additional string.
Claim 3
Dependent Claim
15 words
The device of claim 1 wherein each of said active logic devices is a buffer.
Claim 4
Dependent Claim
15 words
The device of claim 1 wherein each of said active logic devices is an inverter.
Claim 5
Independent Claim
106 words
A device for synchronizing and converting a serial data word of N bits to a parallel data N-bit word comprising: N serially connected delay lines, each said delay line introducing a delay equal to the period of one said data bit; a plurality of flip-flops each having a data input connected to the output of one of said delay lines and also having a clock input; one additional delay line serially connected to said plurality of delay lines, introducing a delay less than the period of one said data bit and having an output connected to the clock input of each of said plurality of flip-flops.
Claim 6
Independent Claim
106 words
A device for synchronizing and converting a serial data word of N bits to a parallel data N-bit word comprising: N serially connected delay lines, each said delay line introducing a delay equal to the period of one said data bit; a plurality of flip-flops each having a data input connected to the output of one of said delay lines and also having a clock input; one additional delay line serially connected to said plurality of delay lines, introducing a delay less than the period of one said data bit and having an output connected to the clock input of each of said plurality of flip-flops.
Claim 7
Dependent Claim
36 words
The device of claim 4 further comprising: one additional flip-flop having a data input connected to the input of one of said N delay lines and clock input connected to said one additional delay line output.
Claim 8
Dependent Claim
18 words
The device of claim 5 wherein each of said delay lines comprises a plurality of active logic devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-28 | 1980-09-27 | 1981-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-28 | 1984-09-27 | 1985-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-28 | 1988-09-27 | 1989-03-29 | $7700.00 | Window Closed / Lapsed |