Abstract This negative resistance network includes a first predetermined channel insulated gate enhancement type field effect transistor having a drain-source path connected to positive and negative input terminals on which a predetermined input voltage is impressed. The gate potential of the first field effect transistor is controlled by a second insulated gate enhancement type field effect transistor having an opposite channel type to the first field effect transistor, a gate connected to the drain thereof which is connected to the predetermined one of the positive and negative input terminals and a source connected to one pole of a dc power supply having a predetermined voltage, and by a third insulated gate enhancement type field effect transistor having the same channel type as the first field effect transistor, a drain and a gate connected to the drain of the second field effect transistor as well as to the gate of the first field effect transistor and a source connected to the source thereof which is connected to the other input terminal as well as to the other pole of the dc power supply, whereby the first field effect transistor shows a negative resistance characteristic attaining a relatively low current consumption over a relatively wide level range of the input voltage.
A negative resistance network having positive and negative input terminals to which a predetermined input voltage is applied comprising a first predetermined channel insulated gate enhancement field effect transistor with a drain-source path connected across the positive and negative input terminals; a second insulated gate enhancement type field effect transistor of an opposite channel type to the first field effect transistor, the gate of the second field effect transistor being connected to the drain of the first field effect transistor and to a predetermined one of the positive and negative input terminals, and the source of the second field effect transistor being connected to one pole of a dc power supply having a predetermined voltage; and a third insulated gate enhancement type field effect transistor of the same channel type as the first field effect transistor, the drain and the gate of the third field effect transistor being connected to the drain of the second field effect transistor and to the gate of the first field effect transistor, and the source of the third field effect transistor being connected to the source of the first field effect transistor, to the other input terminal and to the other pole of the dc power supply.
Claim 2
Dependent Claim
203 words
A negative resistance network having positive and negative input terminals to which a predetermined input voltage is applied comprising a first predetermined channel insulated gate enhancement field effect transistor with a drain-source path connected across the positive and negative input terminals; a second insulated gate enhancement type field effect transistor of an opposite channel type to the first field effect transistor, the gate of the second field effect transistor being connected to the drain of the first field effect transistor and to a predetermined one of the positive and negative input terminals, and the source of the second field effect transistor being connected to one pole of a dc power supply having a predetermined voltage; and a third insulated gate enhancement type field effect transistor of the same channel type as the first field effect transistor, the drain and the gate of the third field effect transistor being connected to the drain of the second field effect transistor and to the gate of the first field effect transistor, and the source of the third field effect transistor being connected to the source of the first field effect transistor, to the other input terminal and to the other pole of the dc power supply.
Claim 3
Dependent Claim
33 words
A negative resistance network as in claim 1 wherein a dc impedance element is connected between the source of the second field effect transistor and the one pole of the dc power supply.
Claim 4
Dependent Claim
29 words
A negative resistance network as in claim 1 wherein a dc impedance element is connected between the one input terminal and the drain of the first field effect transistor.
Claim 5
Dependent Claim
27 words
A negative resistance network as in claim 1 wherein a dc impedance element is connected in parallel with the drain-source path of the first field effect transistor.