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US4013972A Expired / Lapsed US ⏱️ 0.0 years remaining

Amplifier with gain control means

Assignee: NEC Corp
•
Filing: 1976-05-03
•
Granted: 1977-03-22
•
Expires: 1996-05-03
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Abstract

Abstract A gain controllable amplifier of the present invention comprises a first and a second differential amplifier. The first differential amplifier serves as an amplifier for an input signal to be impressed on emitters connected in common with each other, while the second differential amplifier serves as a base bias voltage control circuit of the first differential amplifier. The bias voltage derived from the second differential amplifier is changed by a D.C. bias voltage applied to the bases of the respective transistors in the second differential amplifier. The connected to the respective output terminals of the second differential amplifier are transistors whose bases receive a constant voltage. The gain of the first differential amplifier can be controlled by adjusting the D.C. bias voltage applied to the second differential amplifier. The present invention further comprises two current supply circuit each connected to the aforesaid respective output terminals of the second differential amplifier. When one of the transistors in the second differential amplifier is brought into a cut-off condition, the base bias voltage on the first differential amplifier is supplied directly through a current supply circuit. As a result, a variable range of the base voltage on the second differential amplifier is becomes wider, with a resulting increase in the gain control range of the first differential amplifier, thereby achieving increased attenuation of gain. The amplifier according to the present invention is suited for use as a gain control circuit especially for an audio circuit which requires attenuation to a great degree.

Inventors

  • 👤 Shigeo Nishitoba
  • 👤 Kazuo Tokuda

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 01:18
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023; H03G3/00; H03G3/02; H03G3/04; H03G3/10

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 160 words
An amplifier comprising: a differential amplifier having a common electrode terminal, first and second bias terminals and an output terminal; means for applying an input signal to said common electrode terminal of said differential amplifier; first and second transistors whose emitters are connected to said first and second bias terminals, respectively; third and fourth transistors whose collectors are connected to the respective bases of said first and second transistors; a constant current source coupled to the respective emitters of said third and fourth transistors; fifth and sixth transistors whose emitters are connected to the respective collectors of said third and fourth transistors; a constant voltage source connected to the bases of said fifth and sixth transistors; a bias voltage source impressing a constant voltage on the base of said third transistor; means for applying bias voltage to the base of said fourth transistor; and first and second current supply sources for supplying currents to said first and second transistors, respectively.
Claim 2
Dependent Claim 160 words
An amplifier comprising: a differential amplifier having a common electrode terminal, first and second bias terminals and an output terminal; means for applying an input signal to said common electrode terminal of said differential amplifier; first and second transistors whose emitters are connected to said first and second bias terminals, respectively; third and fourth transistors whose collectors are connected to the respective bases of said first and second transistors; a constant current source coupled to the respective emitters of said third and fourth transistors; fifth and sixth transistors whose emitters are connected to the respective collectors of said third and fourth transistors; a constant voltage source connected to the bases of said fifth and sixth transistors; a bias voltage source impressing a constant voltage on the base of said third transistor; means for applying bias voltage to the base of said fourth transistor; and first and second current supply sources for supplying currents to said first and second transistors, respectively.
Claim 3
Dependent Claim 35 words
An amplifier claimed in claim 1, wherein said first and second current supply sources comprises respectively first and second resistors connected between a voltage supply terminal and respective bases of said first and second transistors.
Claim 4
Dependent Claim 127 words
An amplifier claimed in claim 1, wherein said first and second current supply sources comprise: i. seventh and eighth transistors whose emitters are connected to the respective collectors of said first and second transistors and whose collectors are connected to a power supply line, respectively; ii. ninth and tenth transistors whose bases and collectors are connected to the respective bases of said seventh and eighth transistors, and whose emitters are connected to said power supply line, respectivley; and iii. eleventh and twelveth transistors, whose bases are connected to the respective junctions of the bases and collectors and said ninth and tenth transistors, whose emitters are connected to said power supply line, and whose collectors are connected to the respective bases of said first and second transistors, respectively.
Claim 5
Dependent Claim 80 words
An amplifier claimed in claim 1, further comprising: a second differential amplifier including a common electrode terminal, first and second bias teminals and an output terminal, said first and second transistors being connected to said second and first bias terminals of said second differential amplifier, respectively, and the output terminals of said first and second differential amplifiers being commonly connected with each other, whereby the D.C. potential of an output may not be affected by the adjustment of a gain.
Claim 6
Dependent Claim 27 words
An amplifier claimed im claim 4, wherein a capacitive element of 0.01 to 0.1 μF is connected between the base of said fourth transistor and earth potential.

References Cited (Backward Citations)

US3684974A Cited
US3641450A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-03-21 1980-09-20 1981-03-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-03-21 1984-09-20 1985-03-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-03-21 1988-09-20 1989-03-22 $7700.00 Window Closed / Lapsed

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