Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
345 words
Apparatus, in a receiver, for detecting the mid-pulse phase reversal of an input signal s(t) = a(t) BLT cos (ω 0 t + θ 1 ), where the signal a(t) BLT is a modulating signal a(t) after band-limiting by a transmitter and cos (ω 0 t + θ 1 ) relates to a carrier having a frequency f 0 , comprising: means for generating a signal having a frequency of f 0 ; a hard-limiter whose input is connected to the signal generating means, and whose output is the signal sin (ω 0 t + θ 2 ) hard limited, and θ 2 is the phase change due to the hard limiting; a multiplier circuit, whose two inputs are connected to the input signal s(t) and the output of the hard limiter, the output of the multiplier comprising the signal a(t) BLT plus the sum of higher modulation products; a low-pass filter, whose input is connected to the output of the multiplier and whose output is a(t) BLTR , which is the signal a(t) as modified by the band limiting effects of the transmitter and receiver, the higher modulation products being filtered out by the low-pass filter; a threshold detector, whose input is connected to the output of the low-pass filter, which senses the presence of a received pulse; a delay timing logic circuit, whose input is connected to the output of the threshold detector, for delaying its output signal with respect to its input signal; a comparator, serving the function of a zero crossing detector, whose input is connected to the output of the low-pass filter, which detects the mid-pulse zero crossing of a a(t) BLTR , and therefore of a(t); an AND gate, whose inputs are connected to the outputs of the comparator and of the delay timing logic circuit, and whose output comprises a positive-going pulse whose trailing edge represents the mid-pulse of a(t) BLTR ; and a one-shot, whose input is connected to the output of the AND gate, and whose output is a sharp pulse representing the mid-pulse of a(t).
Claim 2
Dependent Claim
345 words
Apparatus, in a receiver, for detecting the mid-pulse phase reversal of an input signal s(t) = a(t) BLT cos (ω 0 t + θ 1 ), where the signal a(t) BLT is a modulating signal a(t) after band-limiting by a transmitter and cos (ω 0 t + θ 1 ) relates to a carrier having a frequency f 0 , comprising: means for generating a signal having a frequency of f 0 ; a hard-limiter whose input is connected to the signal generating means, and whose output is the signal sin (ω 0 t + θ 2 ) hard limited, and θ 2 is the phase change due to the hard limiting; a multiplier circuit, whose two inputs are connected to the input signal s(t) and the output of the hard limiter, the output of the multiplier comprising the signal a(t) BLT plus the sum of higher modulation products; a low-pass filter, whose input is connected to the output of the multiplier and whose output is a(t) BLTR , which is the signal a(t) as modified by the band limiting effects of the transmitter and receiver, the higher modulation products being filtered out by the low-pass filter; a threshold detector, whose input is connected to the output of the low-pass filter, which senses the presence of a received pulse; a delay timing logic circuit, whose input is connected to the output of the threshold detector, for delaying its output signal with respect to its input signal; a comparator, serving the function of a zero crossing detector, whose input is connected to the output of the low-pass filter, which detects the mid-pulse zero crossing of a a(t) BLTR , and therefore of a(t); an AND gate, whose inputs are connected to the outputs of the comparator and of the delay timing logic circuit, and whose output comprises a positive-going pulse whose trailing edge represents the mid-pulse of a(t) BLTR ; and a one-shot, whose input is connected to the output of the AND gate, and whose output is a sharp pulse representing the mid-pulse of a(t).