Low KVA static AC motor drive

Claim 2

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, capacitance means for storing electrical energy for commutating off said inverter semiconductors, auxiliary charging means connected with said capacitance means for charging said capacitance means to voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses, means connected with said capacitance means and responsive to a first control signal for resonantly reversing the polarity of voltage on said capacitance means, switching means responsive to a second control signal to connect said capacitance means across said dc input busses after reversal of its polarity to apply reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors including means for providing said second control signal later than said first control signal so as to allow time for resonantly reversing said voltage of said capacitance means before said capacitance means is connected across said dc input busses for commutation.

Claim 3

A commutation circuit for an inverter as defined in claim 1 and wherein said means for supplying principal dc power to said dc input busses comprises means for providing variable voltage dc power thereto to affect the amplitude of ac output voltage supplied by said inverter to said load, and wherein said auxiliary charging means comprises means for supplying relatively greater voltage for charging said capacitance means when said principal dc power source provides relatively low voltage than when said principal dc power source provides relatively higher voltage.

Claim 4

A commutation circuit for an inverter as defined in claim 2 and wherein said means for supplying principal dc power to said dc input busses comprises converter means receiving substantially constant ac voltage at its input, and wherein said auxiliary charging means comprises rectification means receiving substantially constant ac voltage at its input for producing substantially constant dc voltage for charging said capacitance means through a delaying filter to a voltage dependent upon the time available between commutation to charge said capacitance means.

Claim 5

A commutation circuit for an inverter as defined in claim 1 and wherein said capacitance means comprises means having first and second terminals and wherein one of said terminals is connected to assume substantially the potential of one of said dc input busses and the other of said terminals is connected to receive current from said auxiliary charging means, and wherein said auxiliary charging means comprises means for providing a dc voltage whose polarity with respect to said one dc input bus is the same as the polarity of the other dc input bus with respect to said one dc bus.

Claim 6

A commutation circuit for an inverter as defined in claim 1 and wherein said means for resonantly reversing the polarity of voltage on said capacitance means includes additional switching means rendered conductive by said first control signal for providing a discharge current path for said capacitance means, and further includes inductance means connected in series with said additional switching means for forcing a continued flow of current after said capacitance means has discharged in order to resonantly reverse the polarity of voltage on said capacitance means.

Claim 7

A commutation circuit for an inverter as defined in claim 1 and wherein each of said means responsive to a first control signal and said switching means responsive to a second control signal includes thyristor means.

Claim 8

A commutation circuit for an inverter as defined in claim 1 and further comprising inductance means, external to said polarity-reversing means and connected in series with said switching means that is responsive to a second control signal, for conducting commutation current to the input of said inverter.

Claim 9

A commutation circuit for an inverter as defined in claim 7 and in which said capacitance means, said switching means responsive to a second control signal, and said inductance means are connected in a series circuit, said series circuit being connected from one to the other of said dc input busses, whereby said inductance means prolongs a flow of capacitive commutation current through said inverter to charge said capacitance means to said first polarity again following commutation of said inverter semiconductors.

Claim 10

A commutation circuit for an inverter as defined in claim 1 and wherein said means for resonantly reversing the polarity of voltage on said capacitance means includes triggerable semiconductor means for conducting current from said capacitance means, and inductance means in series with said triggerable semiconductor means for conducting current from said capacitance means; and wherein said capacitance means, triggerable semiconductor means, and inductance means are connected for backbiasing of said triggerable semiconductor means by said capacitance means after said polarity of voltage on said capacitance means is reversed.

Claim 11

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, first capacitance means for storing electrical energy for commutating off said inverter semiconductors, second capacitance means for storing reactive electrical energy returned from said load, auxiliary charging means connected with said capacitance means for charging said first capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses, means connected with said first capacitance means for resonantly reversing the polarity of voltage on said first capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said first capacitance means, and further including first inductance means connected in series with said first switching means and with said first capacitance means for prolonging the flow of current in said first capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said first capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said first capacitance means across said dc input busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.

Claim 12

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, first capacitance means for storing electrical energy for commutating off said inverter semiconductors, second capacitance means for storing reactive electrical energy returned from said load, auxiliary charging means connected with said capacitance means for charging said first capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses, means connected with said first capacitance means for resonantly reversing the polarity of voltage on said first capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said first capacitance means, and further including first inductance means connected in series with said first switching means and with said first capacitance means for prolonging the flow of current in said first capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said first capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said first capacitance means across said dc input busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.

Claim 13

A commutation circuit for an inverter as defined in claim 10 and wherein said means for supplying principal dc power to said dc input busses comprises means for providing variable voltage dc power thereto to affect the amplitude of ac output voltage supplied by said inverter to said load, and wherein said auxiliary charging means comprises means for supplying relatively greater voltage for charging said first capacitance means when said principal dc power source provides relatively low voltage than when said dc power source provides relatively higher voltage.

Claim 14

A commutation circuit for an inverter as defined in claim 11 and wherein said means for supplying principal dc power to said dc input busses comprises converter means receiving substantially constant ac voltage at its input, and wherein said auxiliary charging means comprises rectification means receiving substantially constant ac voltage at its input for producing substantially constant dc voltage for charging said first capacitance means through a delaying filter to a voltage dependent upon the time available between commutations to charge said first capacitance means.

Claim 15

A commutation circuit for an inverter as defined in claim 10 and wherein said first capacitance means comprises means having first and second terminals and wherein one of said terminals is connected to assume substantially the potential of one of said dc input busses and the other of said terminals is connected to receive current from said auxiliary charging means, and wherein said auxiliary charging means comprises means for providing a dc voltage whose polarity with respect to said one dc input bus is the same as the polarity of the other dc input bus with respect to said one dc bus.

Claim 16

A commutation circuit for an inverter as defined in claim 10 and wherein each of said first and second switching means includes thyristor means.

Claim 17

A commutation circuit for an inverter as defined in claim 1 and further comprising second inductance means external to said polarity-reversing means and connected in series with said switching means that is responsive to a second control signal, for conducting commutation current to the input of said inverter.

Claim 18

A commutation circuit for an inverter as defined in claim 15 and in which said first capacitance means, said switching means responsive to a second control signal, and said second inductance means are connected in a series circuit, said series circuit being connected from one to the other of said dc input busses, whereby said second inductance means prolongs a flow of capacitive commutation current through said inverter to charge said first capacitance means to said first polarity again following commutation of said inverter semiconductors.

Claim 19

A commutation circuit for an inverter as defined in claim 10 and wherein said first switching means includes triggerable semiconductor means and wherein said first capacitance means, said triggerable semiconductor means, and said first inductance means are connected for back-biasing of said triggerable semiconductor means by said first capacitance means after said polarity of voltage on said first capacitance means is reversed.

Claim 20

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, capacitance means for storing electrical energy for commutating off said inverter semiconductors, auxiliary charging means connected with said capacitance means for charging said capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses, means connected with said capacitance means for resonantly reversing the polarity of voltage on said capacitance means including first switching means rendered conductive in response to a first control signal for establishing a polarity reversing current path, second switching means responsive to a second control signal to connect said capacitance means to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors, and wherein said current path established by said first switching means is external to said inverter so that the current in said path by-passes said inverter.

Claim 21

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, capacitance means for storing electrical energy for commutating off said inverter semiconductors, auxiliary charging means connected with said capacitance means for charging said capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses, means connected with said capacitance means for resonantly reversing the polarity of voltage on said capacitance means including first switching means rendered conductive in response to a first control signal for establishing a polarity reversing current path, second switching means responsive to a second control signal to connect said capacitance means to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors, and wherein said current path established by said first switching means is external to said inverter so that the current in said path by-passes said inverter.

Claim 22

A commutation circuit for an inverter as defined in claim 18 and wherein said means for supplying principal dc power to said dc input busses comprises means for providing variable voltage dc power thereto to affect the amplitude of ac output voltage supplied by said inverter to said load.

Claim 23

A commutation circuit for an inverter as defined in claim 18 and wherein said capacitance means comprises means having first and second terminals and wherein one of said terminals is connected to assume substantially the potential of one of said dc input busses and the other of said terminals is connected to receive current from said auxiliary charging means, and wherein said auxiliary charging means comprises means for providing a dc voltage whose polarity with respect to said one dc input bus is the same as the polarity of the other dc input bus with respect to said one dc bus.

Claim 24

A commutation circuit for an inverter as defined in claim 18 and wherein each of said first and second switching means includes thyristor means.

Claim 25

A commutation circuit for an inverter as defined in claim 18 and further comprising second inductance means external to said polarity-reversing means and connected in series with said second switching means for conducting commutation current to the input of said inverter.

Claim 26

A commutation circuit for an inverter as defined in claim 22 and in which said capacitance means, said second switching means and said second inductance means are connected in a series circuit, said series circuit being connected from one to the other of said dc input busses, whereby said second inductance means prolongs a flow of capacitive commutation current through said inverter to charge said capacitance means to said first polarity again following commutation of said inverter semiconductors.

Claim 27

A commutation circuit for an inverter as defined in claim 18 and wherein said means for resonantly reversing the polarity of voltage on said capacitance includes triggerable semiconductor means for conducting current from said capacitance means, and further includes inductance means in series with said triggerable semiconductor means for conducting current from said capacitance means; and wherein said capacitance means, triggerable semiconductor means, and inductance means are connected for backbiasing of said triggerable semiconductor means by said capacitance means after said polarity of voltage on said capacitance means is reversed.

Claim 28

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, first capacitance means for storing electrical energy for commutating off said inverter semiconductors, second capacitance means for storing reactive electrical energy returned from said load, auxiliary charging means connected with said first capacitance means for charging said first capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses and means for charging said first capacitance means to different magnitudes of said voltage of a first polarity in dependence magnitudes of said voltage of a first polarity in dependence upon the amount of time available for such charging between successive commutation events, to provide a greater magnitude of said voltage of a first polarity for relatively longer time intervals than for relatively shorter time intervals, means connected with said first capacitance means for resonantly reversing the polarity of voltage on said first capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said first capacitance means and further including first inductance means connected in series with said first switching means and with said first capacitance means for prolonging the flow of current in said first capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said first capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said first capacitance means across said dc busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.

Claim 29

A commutation circuit for a voltage controlled inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, first capacitance means for storing electrical energy for commutating off said inverter semiconductors, second capacitance means for storing reactive electrical energy returned from said load, auxiliary charging means connected with said first capacitance means for charging said first capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising at least one of said dc input busses and means for charging said first capacitance means to different magnitudes of said voltage of a first polarity in dependence magnitudes of said voltage of a first polarity in dependence upon the amount of time available for such charging between successive commutation events, to provide a greater magnitude of said voltage of a first polarity for relatively longer time intervals than for relatively shorter time intervals, means connected with said first capacitance means for resonantly reversing the polarity of voltage on said first capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said first capacitance means and further including first inductance means connected in series with said first switching means and with said first capacitance means for prolonging the flow of current in said first capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said first capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said first capacitance means across said dc busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.

Claim 30

A commutation circuit for an inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, capacitance means for storing electrical energy for commutating off said inverter semiconductors, auxiliary charging means connected with said capacitance means for charging said capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising means for charging said capacitance means to different magnitudes of said voltage of a first polarity in dependence upon the amount of time available for such charging between successive commutation events, to provide a greater magnitude of said voltage of a first polarity for relatively longer time intervals than for relatively shorter time intervals, and further comprising capacitive filter means for storing energy to reduce the ripple of voltage provided by said auxiliary charging means to said capacitance means, means connected with said capacitance means for resonantly reversing the polarity of voltage on said capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said capacitance means and further including first inductance means connected in series with said first switching means and with said capacitance means for prolonging the flow of current in said capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said capacitance means across said dc input busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.

Claim 31

A commutation circuit for an inverter that has dc input busses of nominal positive and negative polarity and inverter semiconductors periodically triggered into conduction and periodically commutated off by applying voltage of reverse polarity across the dc input busses to supply ac current to a load comprising: means connected with said dc input busses for supplying principal dc power of said nominal polarity thereto, capacitance means for storing electrical energy for commutating off said inverter semiconductors, auxiliary charging means connected with said capacitance means for charging said capacitance means to a voltage of a first polarity before commutation, said auxiliary charging means comprising means for charging said capacitance means to different magnitudes of said voltage of a first polarity in dependence upon the amount of time available for such charging between successive commutation events, to provide a greater magnitude of said voltage of a first polarity for relatively longer time intervals than for relatively shorter time intervals, and further comprising capacitive filter means for storing energy to reduce the ripple of voltage provided by said auxiliary charging means to said capacitance means, means connected with said capacitance means for resonantly reversing the polarity of voltage on said capacitance means, including first switching means rendered conductive in response to a first control signal for providing a path for current from said capacitance means and further including first inductance means connected in series with said first switching means and with said capacitance means for prolonging the flow of current in said capacitance means for resonantly reversing the voltage polarity thereof, second switching means responsive to a second control signal to connect said capacitance means in a conduction path to apply its reverse polarity voltage across said dc input busses for commutation of said inverter semiconductors, said second switching means being arranged to connect said capacitance means across said dc input busses in such a way that said conduction path to said inverter is external to said first inductance means, and control circuit means for providing said first and second control signals in synchronism with the periodic triggering of said inverter semiconductors.