Method and apparatus for reducing phaselock loop FM'ing

Claim 1

Phaselock circuitry having a substantially fixed frequency input signal S IN to be tracked and an input signal S L indicating whether the loop is locked, said phaselock circuitry comprising: first means comprising a loop filter whose filtering characteristic is fixed; second means, including controllable oscillator means, for providing two variable frequency signals S F and S H where the frequency of S F is nominally the same as that of S IN , and the frequency of S H is an odd multiple N of the frequency of S F and thus is nominally an odd multiple N of the substantially fixed frequency of S IN ; and third means, including phase detection means connected for continuously receiving said signal S IN and switching means, said third means also connected for receiving S F , S H , and S L , and providing, in accordance with the loop condition as indicated by S L , to the loop filter input one of two signals S X or S Y , where S X is a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S F , and S Y is a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S H , said signal S X being provided to said loop filter input after S L indicates no-lock and said signal S Y being provided to said loop filter input after S L indicates lock.

Claim 6

A method of operating a phaselock loop containing phase detection means, a loop filter whose filtering characteristic is fixed, and controllable oscillator means, said method reducing the degree of frequency modulation of said oscillator without disturbing said loop filter, said method comprising: providing continuously to said phase detection means an input signal S IN which is to be tracked, S IN being of substantially fixed frequency f IN ; providing an input signal S L which indicates whether the loop is locked; generating a variable frequency signal S F whose frequency f F is nominally the same as f IN and where f F is dependent on the phase between S IN and S F ; generating a variable frequency signal S H having frequency f H which is an odd multiple N of f F and thus is nominally an odd multiple N of said f IN ; and providing, in accordance with the loop condition as indicated by S L , one of two signals S X or S Y to the input of said filter, S X being a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S F , and S Y being a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S H , said signal S X being used as the input to said loop filter while the loop is locking, said signal S Y being used as the input to said loop filter after lock is indicated by S L .

Claim 7

A method of operating a phaselock loop containing phase detection means, a loop filter whose filtering characteristic is fixed, and controllable oscillator means, said method reducing the degree of frequency modulation of said oscillator without disturbing said loop filter, said method comprising: providing continuously to said phase detection means an input signal S IN which is to be tracked, S IN being of substantially fixed frequency f IN ; providing an input signal S L which indicates whether the loop is locked; generating a variable frequency signal S F whose frequency f F is nominally the same as f IN and where f F is dependent on the phase between S IN and S F ; generating a variable frequency signal S H having frequency f H which is an odd multiple N of f F and thus is nominally an odd multiple N of said f IN ; and providing, in accordance with the loop condition as indicated by S L , one of two signals S X or S Y to the input of said filter, S X being a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S F , and S Y being a phase detection means output signal produced by the phase comparison in said phase detection means of said signals S IN and S H , said signal S X being used as the input to said loop filter while the loop is locking, said signal S Y being used as the input to said loop filter after lock is indicated by S L .