Patent US4011470A successfully refreshed from Google Patents.
US4011470A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit utilizing open-base transistor as leakage bypass device
Assignee: Motorola Solutions Inc
•
Filing: 1976-03-25
•
Granted: 1977-03-08
•
Expires: 1996-03-25
Abstract
Abstract A floating base transistor connected within an integrated circuit to provide a high temperature high voltage low current bypass device having the same type of temperature dependence as the leakage current shunted therethrough. The bypass device is connected to provide its I CEO current as a current source through which a parasitic leakage current is diverted which would otherwise produce a base current of an output transistor which is supposed to be in the off condition. The parasitic leakage current includes the I CEO current of an opposite polarity driving transistor in the off condition having its emitter connected to a power supply and its base connected to an input circuit and its collector connected to the base of the output transistor. In one embodiment the floating base transistor is a PNP substrate transistor having its collector connected to ground, its emitter connected to the base of an NPN output transistor, and its base floating. The current of the floating base transistor is greater than the parasitic leakage current of a PNP driving transistor, so the NPN output transistor is held in the off position.
Inventors
- 👤 William Folsom Davis
- 👤 Thomas Marinus Frederiksen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:37
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
121 words
An integrated circuit including first and second power conductors coupled thereto, a first transistor, and a second transistor having a base electrode coupled to input circuit means of said integrated circuit and having its emitter coupled to said first power conductor, and having its base connected to a collector of said first transistor, said first transistor having its emitter coupled to said second power conductor, said integrated circuit comprising open-base transistor means bypassing reverse leakage current flowing in said collector of said first transistor connected directly between said base of said second transistor and said first power conductor for holding said second transistor in an "off" condition over a wide temperature range when said first transistor is in an "off" condition.
Claim 2
Dependent Claim
121 words
An integrated circuit including first and second power conductors coupled thereto, a first transistor, and a second transistor having a base electrode coupled to input circuit means of said integrated circuit and having its emitter coupled to said first power conductor, and having its base connected to a collector of said first transistor, said first transistor having its emitter coupled to said second power conductor, said integrated circuit comprising open-base transistor means bypassing reverse leakage current flowing in said collector of said first transistor connected directly between said base of said second transistor and said first power conductor for holding said second transistor in an "off" condition over a wide temperature range when said first transistor is in an "off" condition.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein the first transistor is an NPN transistor.
Claim 4
Dependent Claim
16 words
The circuit of claim 2 in which the open-base transistor bypass means is a substrate transistor.
Claim 5
Dependent Claim
22 words
The circuit of claim 1 wherein the second transistor is a PNP transistor having its emitter coupled to said power conductor means.
Claim 6
Dependent Claim
24 words
The circuit of claim 1 wherein the open-base transistor is a PNP transistor having its emitter connected to the base of the first transistor.
Claim 7
Dependent Claim
31 words
The circuit of claim 1 wherein the first transistor is an NPN transistor and the open-base transistor is PNP transistor having its emitter connected to the base of the first transistor.
Claim 8
Dependent Claim
32 words
The circuit of claim 1 wherein the first transistor is a NPN transistor and the open-base transistor is an NPN transistor having its collector connected to the base of the first transistor.
Claim 9
Dependent Claim
32 words
The circuit of claim 1 wherein the first transistor is an NPN transistor and the open-base transistor is a PNP transistor having its collector connected to the base of the first transistor.
Claim 10
Dependent Claim
127 words
An integrated circuit comprising first and second power conductors coupled thereto, a first PNP transistor, and a second NPN transistor having a base electrode coupled to input circuit means of said integrated circuit and having its emitter coupled to said first power conductor and having its base connected to a collector of said first PNP transistor, said first PNP transistor having its emitter coupled to a second power conductor, open-base PNP substrate transistor means bypassing reverse leakage current flowing in said collector of said first PNP transistor connected directly between said base of said second NPN transistor and said first power conductor for holding said second NPN transistor in an "off" condition over a wide temperature range when said first PNP transistor is in an "off" condition.
Claim 11
Dependent Claim
127 words
An integrated circuit comprising first and second power conductors coupled thereto, a first PNP transistor, and a second NPN transistor having a base electrode coupled to input circuit means of said integrated circuit and having its emitter coupled to said first power conductor and having its base connected to a collector of said first PNP transistor, said first PNP transistor having its emitter coupled to a second power conductor, open-base PNP substrate transistor means bypassing reverse leakage current flowing in said collector of said first PNP transistor connected directly between said base of said second NPN transistor and said first power conductor for holding said second NPN transistor in an "off" condition over a wide temperature range when said first PNP transistor is in an "off" condition.
References Cited (Backward Citations)
US2991424A
Cited
US3370244A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-07 | 1980-09-06 | 1981-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-07 | 1984-09-06 | 1985-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-07 | 1988-09-06 | 1989-03-08 | $7700.00 | Window Closed / Lapsed |