Synchronous switch control circuit

Claim 2

A switching control circuit for timing the selective energization of a load by an AC power source in response to the actuation of an ON/OFF switch comprising: means for generating pulses having transitions synchronous with the voltage zero-crossings of the AC power source; timing means triggered by said pulse generating means for generating a first timed signal which begins on the occurrence of a positive-going voltage zero-crossing and a second timed signal which begins on the occurrence of a negative-going voltage zero-crossing; output means responsive to said timing means and the actuation of the ON/OFF switch for generating turn-on and turn-off signals, said turn-on signal being generated after the first timing of said first timed signal subsequent the actuation of an ON condition and said turn-off signal being generated after the first timing out of said second timed signal subsequent the actuation of an OFF condition; and switching means for electrically coupling and uncoupling the load from the AC power source in response to said turn-on and turn-off signals, respectively.

Claim 3

The switching control circuit of claim 1 wherein said switching means comprises: a transistor for accepting said turn-on and turn-off signals, said transistor being in a conductive state in the presence of a turn-on signal and being in a non-conductive state in the presence of a turn-off signal; and a relay activated and deactivated by said transistor.

Claim 4

The switching control circuit of claim 2 wherein said output means comprises: a clocked two-state device for generating and maintaining said turn-on and turn-off signals, said signals changing from one to the other only on the application of a clock pulse to said clocked two-state device; and clocking means cooperating with said timing means and said clocked two-state device for generating clock pulses which are selectively applied to said two-state device upon the timing out of said first timed signal if said two-state device is generating a turn-off signal or which are applied to said two-state device upon the timing out of said second timed signal if said two-state device is generating a turn-on signal.

Claim 5

The switching control circuit of claim 3 wherein said timing means comprises: a first one-shot device which is positively triggered by positive-going transitions of the pulses from said pulse generating means; a second one-shot device which is positively triggered by pulses which are the inverse of the pulses from said pulse generating means; and means interposed between said pulse generating means and said second one-shot device for inverting the pulses from said pulse generating means.

Claim 6

The switching control circuit of claim 4 wherein said first one-shot has its negative input connected to ground and said second one-shot has said turn-on and turn-off signals applied to its negative input, said turn-off signal preventing said second one-shot from being positively triggered by said inverted pulses.

Claim 7

The switching circuit of claim 5 wherein said clocking means comprises: a first dual input NAND gate for accepting said first timed signals as one input and said turn-on and turn-off signals as another input; a second dual input NAND gate having a first input for accepting the output from said first dual input nand gate; a first inverter coupled between said second one-shot and said first input of said second NAND gate for applying inverted second timed signals to said second NAND gate; a second inverter having as its input the output of said first inverter; an RC network coupling the output of said second inverter to the second input of said second NAND gate, said RC network comprising a resistor connected between the output of said second inverter and the second input of said second NAND gate and a capacitor connected between the second input of said second NAND gate and ground; and a third inverter for coupling the output of said second NAND gate to said clocked two-state device.

Claim 8

A switching control circuit for timing the selective energization of a load by an AC power source in response to the actuation of an ON/OFF switch comprising: means for generating pulses having transitions synchronous with the voltage zero-crossings of the AC power source; first timing means triggered by said pulse generating means for generating a first timed signal of predetermined duration on the occurrence of a positive-going voltage zero-crossing; second timing means triggered by said pulse generating means for generating a second timed signal of predetermined duration on the occurrence of a negative-going voltage zero-crossing; output means responsive to the actuation of the ON/OFF switch and said first and second timed signals for generating a turn-on signal and a turn-off signal, said turn-on signal being generated when said first timed signal times out subsequent the actuation of an ON condition and said turn-off signal being generated when said second timed signal times out subsequent the actuation of an OFF condition; and switching means for electrically coupling the load to the AC power source in response to said turn-on signal and for electrically uncoupling the load from the AC power source in response to said turn-off signal.

Claim 9

A switching control circuit for timing the selective energization of a load by an AC power source in response to the actuation of an ON/OFF switch comprising: means for generating pulses having transitions synchronous with the voltage zero-crossings of the AC power source; first timing means triggered by said pulse generating means for generating a first timed signal of predetermined duration on the occurrence of a positive-going voltage zero-crossing; second timing means triggered by said pulse generating means for generating a second timed signal of predetermined duration on the occurrence of a negative-going voltage zero-crossing; output means responsive to the actuation of the ON/OFF switch and said first and second timed signals for generating a turn-on signal and a turn-off signal, said turn-on signal being generated when said first timed signal times out subsequent the actuation of an ON condition and said turn-off signal being generated when said second timed signal times out subsequent the actuation of an OFF condition; and switching means for electrically coupling the load to the AC power source in response to said turn-on signal and for electrically uncoupling the load from the AC power source in response to said turn-off signal.

Claim 10

The switching control circuit of claim 7 wherein said switching means comprises: a transistor for accepting said turn-on and turn-off signals, said transistor being in a conductive state when said turn-on signal is present and being in a non-conductive state when said turn-off signal is present; and a relay activated and deactivated by said transistor.

Claim 11

The switching control circuit of claim 8 wherein said output means comprises: a clocked two-state device for generating and maintaining said turn-on and turn-off signals, said signals changing from one to the other only on the application of a clock pulse to said clocked two-state device; and clocking means cooperating with said timing means and said clocked two-state device for generating clock pulses which are selectively applied to said two-state device upon the timing out of said first timed signal if said two-state device is generating a turn-off signal or which are applied to said two-state device upon the timing out of said second timed signal if said two-state device is generating a turn-on signal.

Claim 12

The switching control circuit of claim 9 wherein said first timing means comprises a first one-shot device which is positively triggered by positive-going transitions of the pulses from said pulse generating means, said first one-shot having its negative input at a constant ground potential.

Claim 13

The switching control circuit of claim 10 wherein said second timing means comprises: a second one-shot device which is positively triggered by positive-going input pulses which are the inverse of negative-going pulses generated by said pulse generating means, said second one-shot accepting at its negative input said turn-on and turn-off signals and capable of being triggered only when said turn-on signal is present; and means coupled between said pulse generating means and said second one-shot device for inverting the pulses from said pulse generating means.

Claim 14

The switching control circuit of claim 11 wherein said clocking means comprises: a first dual input NAND gate for accepting said first timed signals as one input and said turn-on and turn-off signals as another input; a second dual input NAND gate having a first input for accepting the output from said first dual input NAND gate; a first inverter coupled between said second one-shot and said first input of said second NAND gate for applying inverted second timed signals to said second NAND gate; a second inverter having as its input the output of said first inverter; an RC network coupling the output of said second inverter to the second input of said second NAND gate, said RC network comprising a resistor connected between the output of said second inverter and the second input of said second NAND gate and a capacitor connected between the second input of said second NAND gate and ground; and a third inverter for coupling the output of said second NAND gate to said clocked two-state device.

Claim 15

A switching control circuit for selectively timing the energization of a load by an AC power source in response to the actuation of an ON/OFF switch comprising: means for generating pulses synchronous with the zero-crossings of the voltage of the AC power source, said pulses having positive-going leading edges synchronous with the positive-going zero-crossings and negative-going trailing edges synchronous with the negative-going zero-crossings; first timing means triggered by said pulse generating means for generating a first timed signal in response to said leading edges; second timing means triggered by said pulse generating means for generating a second timed signal in response to said trailing edges; clocked latching means responsive to the actuation of the ON/OFF switch for generating turn-on and turn-off signals upon the application of clock pulses, said turn-on signal being generated on the application of a clock pulse subsequent the actuation of an ON condition and said turn-off signal being generated on the application of a clock pulse subsequent the actuation of an OFF condition, either of said turn-on and turn-off signals being maintained until the application of a clock pulse subsequent the actuation of a condition of the ON/OFF switch which would change the signal generated by said latching means; clocking means cooperating with said first and second timing means and rsponsive to the signals generated by said latching means for applying clock pulses to said latching means, said clock pulses being applied after said first timed signal times out if said latching means is generating a turn-off signal or after said second timed signal times out if said latching means is generating a turn-on signal; and switching means responsive to said turn-on and turn-off signals generated by said latching means for electrically coupling the load to the AC source in response to a turn-on signal and for uncoupling the load from the AC source in response to a turn-off signal.

Claim 16

A switching control circuit for selectively timing the energization of a load by an AC power source in response to the actuation of an ON/OFF switch comprising: means for generating pulses synchronous with the zero-crossings of the voltage of the AC power source, said pulses having positive-going leading edges synchronous with the positive-going zero-crossings and negative-going trailing edges synchronous with the negative-going zero-crossings; first timing means triggered by said pulse generating means for generating a first timed signal in response to said leading edges; second timing means triggered by said pulse generating means for generating a second timed signal in response to said trailing edges; clocked latching means responsive to the actuation of the ON/OFF switch for generating turn-on and turn-off signals upon the application of clock pulses, said turn-on signal being generated on the application of a clock pulse subsequent the actuation of an ON condition and said turn-off signal being generated on the application of a clock pulse subsequent the actuation of an OFF condition, either of said turn-on and turn-off signals being maintained until the application of a clock pulse subsequent the actuation of a condition of the ON/OFF switch which would change the signal generated by said latching means; clocking means cooperating with said first and second timing means and rsponsive to the signals generated by said latching means for applying clock pulses to said latching means, said clock pulses being applied after said first timed signal times out if said latching means is generating a turn-off signal or after said second timed signal times out if said latching means is generating a turn-on signal; and switching means responsive to said turn-on and turn-off signals generated by said latching means for electrically coupling the load to the AC source in response to a turn-on signal and for uncoupling the load from the AC source in response to a turn-off signal.

Claim 17

The switching circuit of claim 13 wherein said switching means comprises: a transistor for accepting said turn-on and turn-off signals, said transistor being in a conductive state in the presence of a turn-on signal and being in a non-conductive state in the presence of a turn-off signal; and a relay activated and deactivated by said transistor.

Claim 18

The switching circuit of claim 14 wherein said first timing means comprises a first one-shot device which is positively triggered by positive-going input pulses which are received directly from said synchronous pulse generating means.

Claim 19

The switching circuit of claim 15 wherein said second timing means comprises: a second one-shot device which is positively triggered by positive-going input pulses which are the inverse of negative-going pulse generated by said synchronous pulse generating means, said second one-shot accepting of its negative input said turn-on and turn-off signals and capable of being triggered only when said turn-on signal is present; and inverting means coupled between said pulse generating means and said second one-shot for inverting the pulses generated by said pulse generating means.

Claim 20

The switching control circuit of claim 16 wherein said clocking means comprises: a first dual input NAND gate for accepting said first timed output as one input and said turn-on and turn-off signals as another input; a second dual input NAND gate having a first input for accepting the output from said first dual input NAND gate; a first inverter coupled between said second one-shot and said first input of said second NAND gate for applying inverted second timed signals to said second NAND gate; a second inverter having as its input the output of said first inverter; an RC network coupling the output of said second inverter to the second input of said second NAND gate, said RC network comprising a resistor connected between the output of said second inverter and the second input of said second NAND gate and a capacitor connected between the second input of said second NAND gate and ground; and a third inverter for coupling the output of said second NAND gate to said clocked two-state device.