Patent US4009397A successfully refreshed from Google Patents.
US4009397A
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US
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Logic circuit
Assignee: US Philips Corp
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Filing: 1975-08-06
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Granted: 1977-02-22
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Expires: 1995-08-06
Abstract
Abstract A logic circuit in I 2 L wherein across the base-emitter paths of the NPN-transistors diodes are connected in order to reduce the propagation delay time of the logic circuit.
Inventors
- 👤 Cornelis Mulder
- 👤 Henricus Elisabeth Jozef Wulms
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/02; H03K19/08; H03K19/082; H03K19/091
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
217 words
A logic gate circuit, comprising a first group of transistors each having emitter, base and collector, means connecting in parallel one of the base-emitter and collector-emitter paths of the transistors in the first group, a second group of transistors each having emitter, base and collector, means connecting in parallel the base-emitter paths of the transistors in the second group to the collector-emitter path of at least one of the transistors of the first group, a current source for biasing the transistors of the first group and coupled to a common connection point of the emitters of the transistors of the first group, a current source for biasing the transistors of the second group and coupled to a common connection point of the emitters of the transistors of the second group, each of the bases of the transistors of the first and the second group being connected respectively to the current source for the transistors of the first and the second group, and means providing between the base and the emitter of each of the transistors of the first and second groups a current path for sinking a part of the current which is supplied by the current source which is connected to the base of each said transistor when each said transistor is in the conductive state.
Claim 2
Dependent Claim
217 words
A logic gate circuit, comprising a first group of transistors each having emitter, base and collector, means connecting in parallel one of the base-emitter and collector-emitter paths of the transistors in the first group, a second group of transistors each having emitter, base and collector, means connecting in parallel the base-emitter paths of the transistors in the second group to the collector-emitter path of at least one of the transistors of the first group, a current source for biasing the transistors of the first group and coupled to a common connection point of the emitters of the transistors of the first group, a current source for biasing the transistors of the second group and coupled to a common connection point of the emitters of the transistors of the second group, each of the bases of the transistors of the first and the second group being connected respectively to the current source for the transistors of the first and the second group, and means providing between the base and the emitter of each of the transistors of the first and second groups a current path for sinking a part of the current which is supplied by the current source which is connected to the base of each said transistor when each said transistor is in the conductive state.
Claim 3
Dependent Claim
46 words
A logic gate circuit as claimed in claim 1, wherein the current path for sinking part of the current source comprises a diode whose forward direction is the same as the forward direction of the base-emitter diode of each said transistor connected to the current source.
Claim 4
Dependent Claim
41 words
A logic gate circuit as claimed in claim 2, wherein the diode is constituted by a transistor whose base and collector are interconnected, the effective emitter area of said transistor being smaller than the effective emitter area of each said transistor.
Claim 5
Dependent Claim
18 words
A logic gate circuit as claimed in claim 1, wherein the current path is constituted by a resistance.
Claim 6
Dependent Claim
50 words
A logic gate circuit as claimed in claim 1, wherein the transistors of the first and the second group are of the NPN-type and the current sources each comprise a lateral PNP-transistor, and a resistor connects the base of the lateral PNP-transistor to the emitters of the transistors it biases.
Claim 7
Dependent Claim
19 words
A logic gate circuit as claimed in claim 2, wherein a resistance is included in series with the diode.
References Cited (Backward Citations)
US3509364A
Cited
US3816758A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-22 | 1980-08-23 | 1981-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-22 | 1984-08-23 | 1985-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-22 | 1988-08-23 | 1989-02-22 | $7700.00 | Window Closed / Lapsed |