Transistor having an emitter with a low impurity concentration portion and a high impurity concentration portion

Claim 2

A semiconductor device comprising: a. a first semiconductor region of a first conductivity type; b. a second semiconductor region of the opposite conductivity type interfaced with said first region, and forming a first PN junction therewith; c. a third semiconductor region of said first conductivity type interfaced with said second region and forming a second PN junction therewith lying on the opposite side of said second region from said first region; d. means for forwardly biasing said first PN junction and transporting majority carriers in said first region to said third region; e. said first region having a lightly doped portion adjacent to said first PN junction and a heavily doped portion forming a third junction between said lightly doped portion and said heavily doped portion; f. said third junction being situated from said first PN junction by a distance less than the diffusion length of minority carriers in said lightly doped portion; and g. the impurity concentration and gradient at said third junction being selected to have an electric field such that a drift current of minority carriers produced thereby substantially balances a diffusion current of minority carriers injected from said first PN junction.

Claim 3

A semiconductor device comprising: a. a first semiconductor region of a first conductivity type; b. a second semiconductor region of the opposite conductivity type interfaced with said first region, and forming a first PN junction therewith; c. a third semiconductor region of said first conductivity type interfaced with said second region and forming a second PN junction therewith lying on the opposite side of said second region from said first PN junction; d. means for forwardly biasing said first PN junction and transporting majority carriers in said first region to said third region; e. said first region having a lightly doped portion adjacent to said first PN junction and a heavily doped portion forming a third junction between said lightly doped portion and said heavily doped portion; f. said third junction being situated from said first PN junction by a distance less than the diffusion length L of minority carriers in said lightly doped portion; and g. the structure of the said device producing an electric field at said third junction of which the value is larger than (kT/qL), where k is Boltzmann's constant, T is the temperature, and q is the charge of the electron.

Claim 4

A semiconductor device comprising: a. a first semiconductor region of a first conductivity type; b. a second semiconductor region of the opposite conductivity type interfaced with said first region, and forming a first PN junction therewith; c. a third semiconductor region of said first conductivity type interfaced with said second region and forming a second PN junction therewith lying on the opposite side of said second region from said first PN junction; d. means for forwardly biasing said first PN junction and transporting majority carriers in said first region to said third region; e. said first region having a lightly doped portion adjacent to said first PN junction and a heavily doped portion forming a third junction between said lightly doped portion and said heavily doped portion; f. said third junction being situated from said first PN junction by a distance less than the diffusion length L of minority carriers in said lightly doped portion; and g. the structure of the said device producing an electric field at said third junction of which the value is larger than (kT/qL), where k is Boltzmann's constant, T is the temperature, and q is the charge of the electron.

Claim 5

A semiconductor device according to claim 1, in which said second region has a second lightly doped portion and a second heavily doped portion surrounding said second lightly doped portion and forming a fourth junction therewith.

Claim 6

A semiconductor device according to claim 1, further having a fourth semiconductor region of said opposite conductivity type interfaced with said third region and forming a fourth PN junction therewith lying on the opposite side of said third region from said second PN junction.

Claim 7

A semiconductor device according to claim 1, in which said third region has a second lightly doped portion adjacent to said second PN junction and a second heavily doped portion forming a fourth junction between said second lightly doped portion and said second heavily doped portion.

Claim 8

A semiconductor device comprising: a. a first semiconductor region of a first conductivity type; b. a second semiconductor region of a second conductivity type interfaced with said first region; c. a third semiconductor region of the first conductivity interfaced with said second region and on the opposite side of said second region from said first region; d. voltage applying means for transporting majority carriers in said first region to said third region; e. said first region having a lightly doped portion adjacent to said second region and a heavily doped portion forming a third junction between said lightly doped portion and said heavily doped portion; f. said third junction being situated from said second region by a distance less than the diffusion length of minority carriers injected into said lightly doped portion from said second region; g. the structure of the said device providing a potential barrier across said third junction of which the value is larger than 0.1 eV; and h. the structure of the said device producing a built-in-field at said third junction of which the value is larger than 10 3 V/cm.

Claim 9

A semiconductor device comprising: a. a first semiconductor region of a first conductivity type; b. a second semiconductor region of a second conductivity type interfaced with said first region; c. a third semiconductor region of the first conductivity interfaced with said second region and on the opposite side of said second region from said first region; d. voltage applying means for transporting majority carriers in said first region to said third region; e. said first region having a lightly doped portion adjacent to said second region and a heavily doped portion forming a third junction between said lightly doped portion and said heavily doped portion; f. said third junction being situated from said second region by a distance less than the diffusion length of minority carriers injected into said lightly doped portion from said second region; g. the structure of the said device providing a potential barrier across said third junction of which the value is larger than 0.1 eV; and h. the structure of the said device producing a built-in-field at said third junction of which the value is larger than 10 3 V/cm.

Claim 10

A semiconductor junction transistor comprising a first region forming an emitter, a second region forming a base, and a third region forming a collector, said first region being of a first conductivity type which is interfaced with said second region to provide a first PN junction, said second region being of a conductivity type opposite said emitter region which is interfaced with said third region to provide a second PN junction substantially parallel to said first PN junction, said third region being of the same conductivity type as said first region, a fourth region of high impurity concentration of the same impurity type as said first region formed in the outer face of said first region and which forms a third junction between said fourth region and said first region, said first, second and third regions having terminal contacts for circuit connections, said third junction being spaced generally parallel to said first junction by a distance which is shorter than the diffusion length of minority carriers injected into said first region from said second region, the thickness dimension of said first region being two to five times the thickness dimension of said fourth region, said fourth region having an impurity concentration of approximately 10 20 atoms/cm 3 at the outer surface, and said impurity concentration of said first region being less than 10 18 atoms/cm 3 .

Claim 11

A semiconductor junction transistor comprising a first region forming an emitter, a second region forming a base, and a third region forming a collector, said first region being of a first conductivity type which is interfaced with said second region to provide a first PN junction, said second region being of a conductivity type opposite said emitter region which is interfaced with said third region to provide a second PN junction substantially parallel to said first PN junction, said third region being of the same conductivity type as said first region, a fourth region of high impurity concentration of the same impurity type as said first region formed in the outer face of said first region and which forms a third junction between said fourth region and said first region, said first, second and third regions having terminal contacts for circuit connections, said third junction being spaced generally parallel to said first junction by a distance which is shorter than the diffusion length of minority carriers injected into said first region from said second region, the thickness dimension of said first region being two to five times the thickness dimension of said fourth region, said fourth region having an impurity concentration of approximately 10 20 atoms/cm 3 at the outer surface, and said impurity concentration of said first region being less than 10 18 atoms/cm 3 .