Patent US4006469A successfully refreshed from Google Patents.
US4006469A
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Data storage cell with transistors operating at different threshold voltages
Assignee: International Business Machines Corp
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Filing: 1975-12-16
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Granted: 1977-02-01
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Expires: 1995-12-16
Abstract
Abstract A semiconductor memory or storage circuit includes cross coupled transistors and isolating transistors operating at a first threshold voltage and load transistors for the cross coupled transistors operating at a second threshold voltage. The storage cell is disposed in a matrix of word and bit lines. The load devices are connected between a supply voltage and the cross coupled transistors which are returned to a reference potential. The isolating transistors are connected between the cross coupled transistors and adjacent bit lines. The word line is connected to the gates of both the isolating transistors and the load devices. When the word line is down, the isolating transistors are turned off and the load devices supply sufficient current to retain the stored information in the cross coupled transistors. When the word line is raised, the gate voltage of the load transistors is raised to supply additional current to the circuit. Simultaneously, the isolating transistors connect the circuit to the bit lines for Read/Write modes of operation. The invention achieves cell powering without a pulse power gate terminal. Also, the invention does not require a special deselect potential to keep current in the circuit during the storage mode.
Inventors
- 👤 Gerald W. Leehan
- 👤 Sylvester F. Miniter, III
- 👤 Augustus J. Sassa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8311
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
83 words
A memory array comprising a. a matrix comprising M word lines and N bit lines or pairs of bit lines, b. a storage circuit between each intersecting word line and pair of bit lines, c. power supply means for each storage circuit, d. means for providing potentials to the word and bit lines, and e. means included in each storage circuit responsive to the word line potentials for controlling the input power to the storage circuit during the active and passive state thereof.
Claim 2
Dependent Claim
83 words
A memory array comprising a. a matrix comprising M word lines and N bit lines or pairs of bit lines, b. a storage circuit between each intersecting word line and pair of bit lines, c. power supply means for each storage circuit, d. means for providing potentials to the word and bit lines, and e. means included in each storage circuit responsive to the word line potentials for controlling the input power to the storage circuit during the active and passive state thereof.
Claim 3
Dependent Claim
28 words
The memory array of claim 1 wherein the means responsive to the word line potentials are at least first and second transistors that operate at different threshold potentials.
Claim 4
Dependent Claim
18 words
The memory array of claim 2 wherein the first and second transistors are depletion and enhancement type, respectively.
Claim 5
Dependent Claim
39 words
The memory array of claim 3 wherein a first potential on the word line operates the depletion devices to supply power to the storage circuit and operates the enhancement devices to disconnect the storage circuit from the bit lines.
Claim 6
Dependent Claim
35 words
The memory array of claim 3 wherein a second potential on the word line increases conduction through the depletion devices and turns on the enhancement devices to connect the storage circuit to the bit lines.
Claim 7
Dependent Claim
17 words
The memory of claim 5 further including a precharge circuit connected between each pair of bit lines.
Claim 8
Dependent Claim
82 words
A memory circuit comprising a. a first and second load transistors that conduct at a first threshold voltage, b. third and fourth storage circuit transistors connected to the load transistors and conducting at a second threshold voltage, c. the fifth and sixth isolating transistors connected to the load and storage circuits and conducting at the second threshold voltage, d. and means for providing first and second threshold potentials to the load and isolating transistors for controlling the power to the storage transistors.
Claim 9
Dependent Claim
82 words
A memory circuit comprising a. a first and second load transistors that conduct at a first threshold voltage, b. third and fourth storage circuit transistors connected to the load transistors and conducting at a second threshold voltage, c. the fifth and sixth isolating transistors connected to the load and storage circuits and conducting at the second threshold voltage, d. and means for providing first and second threshold potentials to the load and isolating transistors for controlling the power to the storage transistors.
Claim 10
Dependent Claim
26 words
The memory circuit of claim 7 wherein the first potential places the load transistors in a conducting condition and the isolating transistors in a non-conducting condition.
Claim 11
Dependent Claim
27 words
The memory circuit of claim 7 wherein the second potential increase the conducting condition of the load transistors and places the isolating transistors in a conducting condition.
Claim 12
Dependent Claim
29 words
The memory circuit of claim 7 wherein the load transistors are depletion type including control electrodes and both the storage and isolating transistors are enhancement type including control electrodes.
Claim 13
Dependent Claim
24 words
The memory circuit of claim 10 wherein the means for providing potentials is connected to the control electrodes of the load and isolating transistors.
Claim 14
Dependent Claim
102 words
A memory circuit comprising a. a pair of bit lines, b. a word line, c. power supply and return line terminals, d. a set of depletion type devices connected at a first, second and third electrodes to a power supply, word line, and common node, respectively, e. a first pair of enhancement devices having their first and second terminals cross coupled and connected to the common nodes and their third electrode connected to the return terminal, and f. a second pair of enhancement type transistors having their first, second and third electrodes connected to the common node, word line and bit line.
Claim 15
Dependent Claim
102 words
A memory circuit comprising a. a pair of bit lines, b. a word line, c. power supply and return line terminals, d. a set of depletion type devices connected at a first, second and third electrodes to a power supply, word line, and common node, respectively, e. a first pair of enhancement devices having their first and second terminals cross coupled and connected to the common nodes and their third electrode connected to the return terminal, and f. a second pair of enhancement type transistors having their first, second and third electrodes connected to the common node, word line and bit line.
Claim 16
Dependent Claim
19 words
The memory array of claim 1 wherein the storage circuit is defined by the memory circuit of claim 12.
Claim 17
Dependent Claim
155 words
A semiconductor device comprising a. a semiconductor substrate, b. first, second and third sets of transistors formed in the substrate in first and second groups, c. diffusion rails formed in the substrate between the first and second groups and serving as bit lines connected to the third transistor in each group, d. first metalization disposed on the substrate and connected to the first set of transistors for supplying power to the groups of transistors, e. second metalization disposed on the substrate and connected to the second set of transistors as a power return for the groups of transistors, f. third metalization disposed on the substrate for interconnecting the second set of devices as a storage circuit, and g. fourth metalization disposed on the substrate and connected to the first and third sets of devices for controlling the power to the storage circuits and the connection of the third set of devices to the bit lines.
Claim 18
Dependent Claim
155 words
A semiconductor device comprising a. a semiconductor substrate, b. first, second and third sets of transistors formed in the substrate in first and second groups, c. diffusion rails formed in the substrate between the first and second groups and serving as bit lines connected to the third transistor in each group, d. first metalization disposed on the substrate and connected to the first set of transistors for supplying power to the groups of transistors, e. second metalization disposed on the substrate and connected to the second set of transistors as a power return for the groups of transistors, f. third metalization disposed on the substrate for interconnecting the second set of devices as a storage circuit, and g. fourth metalization disposed on the substrate and connected to the first and third sets of devices for controlling the power to the storage circuits and the connection of the third set of devices to the bit lines.
Claim 19
Dependent Claim
32 words
The semiconductor device of claim 14 wherein the first set of transistors are depletion mode field effect transistors and the second and third set of transistors are enhancement mode field effect transistors.
References Cited (Backward Citations)
US3949382A
Cited
US3959781A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-01 | 1980-08-02 | 1981-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-01 | 1984-08-02 | 1985-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-01 | 1988-08-02 | 1989-02-01 | $7700.00 | Window Closed / Lapsed |