Abstract A switching arrangement for a data transmission system is described wherein the switching arrangement extends the receiver stop pulse length in time division multiplex transmissions of telegraph signals on a character frame basis. The character frame contains one start pulse, a number m code bits and one stop pulse. The time division multiplex (TDM) signal is applied to a first bistable circuit, and the output signal of the first bistable circuit is applied to a second bistable circuit from which a data signal is emitted to a data sink. A shift register is provided having no fewer than m+3 storage cells in which a first binary digit is stored if a stop signal is applied by means of parallel input terminals to the shift register. Timing pulses applied to the shift register are received in a pulse input. A shift register further includes a serial input terminal over which a second binary digit is read-in where no stop signal is present. A gate having inputs to which are applied the input signal of the m+3 th storage cell of the shift register and the output signal of the first bistable circuit. The gate produces a stop signal. A counter is provided to which are applied the stop signal as a count signal and the output signal of the m+3 th storage cell as a reset signal. The counter produces counter reading signals indicating the reading of the counter. A clock generator or more phase shifted signals are emitted in a square wave pulse form of which one half the unit element length are displaced in proper phase relation by fractions of the unit element length. Phase shifted clock signals as a function of the reading of the counter are used for timing the second bistable circuit.
In a data transmission system having a switching arrangement for extending the receiver stop pulse length for time division multiplex (TDM) transmissions of telegraph signals on a character frame basis, each character frame having a start pulse, a number m code bits and one stop pulse, wherein a TDM signal is applied to a first bistable circuit and the output of the first bistable circuit is applied to a second bistable circuit from which a data signal is emitted to a data sink, the improvement comprising: shift register means having at least a number m+3 storage cells, parallel input terminals receiving a stop signal, a clock pulse input terminal receiving clock pulses to be applied to said shift register means and a serial input terminal receiving a second binary digit whenever no stop signal is present, gate means having input terminals for receiving an output signal from the m+3th storage cell of said shift register means and an output signal from said first bistable circuit, the gate means having an output terminal for producing stop signal, counter means for receiving said stop signal as a signal to be counted and the output signal from the m+3th storage cell of said shift register means as a reset signal, said counter means producing counter reading signals for indicating the reading of said counter means and means for producing phase shifted clock signals one of which is used as a function of the reading of said counter means for timing said second bistable circuit.
Claim 2
Dependent Claim
251 words
In a data transmission system having a switching arrangement for extending the receiver stop pulse length for time division multiplex (TDM) transmissions of telegraph signals on a character frame basis, each character frame having a start pulse, a number m code bits and one stop pulse, wherein a TDM signal is applied to a first bistable circuit and the output of the first bistable circuit is applied to a second bistable circuit from which a data signal is emitted to a data sink, the improvement comprising: shift register means having at least a number m+3 storage cells, parallel input terminals receiving a stop signal, a clock pulse input terminal receiving clock pulses to be applied to said shift register means and a serial input terminal receiving a second binary digit whenever no stop signal is present, gate means having input terminals for receiving an output signal from the m+3th storage cell of said shift register means and an output signal from said first bistable circuit, the gate means having an output terminal for producing stop signal, counter means for receiving said stop signal as a signal to be counted and the output signal from the m+3th storage cell of said shift register means as a reset signal, said counter means producing counter reading signals for indicating the reading of said counter means and means for producing phase shifted clock signals one of which is used as a function of the reading of said counter means for timing said second bistable circuit.
Claim 3
Dependent Claim
76 words
The improved switching arrangement defined in claim 1 wherein n counter reading signals of said counter means indicate the counter reading in the 1-out-of-n code and further comprising: other gate means, each having first input terminals for receiving said counter reading signal and second input terminals for receiving said phase shifted clock signals and means for combining the outputs of said other gates into one additional clock signal which serves to time said second bistable circuit.