Programmable cryptic device for enciphering and deciphering data

Claim 2

An encryptor for encoding a string of data bits comprising in combination: a. register means for generating a pseudo-random bit sequence; b. non-linear generator means comprising logic means for sequentially receiving portions of the pseudo-random bit sequence and for logically combining bits from the portions of the received pseudo-random bit sequence to provide a plurality of combined bit signals, and parity generator means connected to receive said plurality of combined bit signals for providing said non-linear pseudo-random bit sequence with each bit of said sequence being indicative of the parity of the plurality of combined bit signals; c. combining means for combining the data bits of said string of data bits with bits of said non-linear pseudo-random bit sequence to provide a partially encoded signal; and d. shuffle means for receiving said partially encoded signal and for shuffling the bit positions of said partially encoded signal to provide an encoded signal.

Claim 3

The encrypter according to claim 1 wherein said register means is comprised of: a. a multiple stage shift register; and b. feedback means for combining the output of selected stages of said shift register and for feeding said combined output back to the input of said shift register.

Claim 4

The encrypter according to claim 1 wherein said shuffle means is comprised of: a. a multiple stage shift register each stage of which has an input and an output terminal; and b. programming means for selectively connecting the input terminal of selected stages to the output terminal of selected stages so as to shuffle the bit positions of said partially encoded signal.

Claim 5

A cryptic device for encoding a string of data bits comprising in combination: a. a multi-stage shift register; b. feedback means for combining the outputs of selected stages of said shift register and for feeding the combined outputs back to the input of said shift register; c. a plurality of non-linear logic means comprising; a plurality of logic gates corresponding in number to one-half the plurality of inputs to a non-linear logic means, each of said logic gates having an output and at least first and second inputs, the first input of each of said plurality of logic gates being input to said non-linear logic means; a plurality of inverters corresponding in number to said plurality of logic gates, each having an input and and output, the output of each inverter connected to said second input of an associated logic gate with the input of each of said inverters being an input to said non-linear logic means; a parity generator receiving as inputs the outputs from said plurality of logic gates for providing a combined output signal indicative of the parity of the outputs from said plurality of logic gates; d. programmable means for connecting the outputs of selected stages of said multi-stage shift register to selected inputs of said plurality of non-linear logic means; e. means for logically combining the string of data bits with the combined output of a selected one of said plurality of non-linear logic means to provide a partially encoded data bit signal; and f. shuffle means for sequentially receiving blocks of the partially encoded data bit signal and for programmably shuffling the data bit positions within each of the sequentially received blocks of data bits to provide a fully encoded data bit string.

Claim 6

A cryptic device for encoding a string of data bits comprising in combination: a. a multi-stage shift register; b. feedback means for combining the outputs of selected stages of said shift register and for feeding the combined outputs back to the input of said shift register; c. a plurality of non-linear logic means comprising; a plurality of logic gates corresponding in number to one-half the plurality of inputs to a non-linear logic means, each of said logic gates having an output and at least first and second inputs, the first input of each of said plurality of logic gates being input to said non-linear logic means; a plurality of inverters corresponding in number to said plurality of logic gates, each having an input and and output, the output of each inverter connected to said second input of an associated logic gate with the input of each of said inverters being an input to said non-linear logic means; a parity generator receiving as inputs the outputs from said plurality of logic gates for providing a combined output signal indicative of the parity of the outputs from said plurality of logic gates; d. programmable means for connecting the outputs of selected stages of said multi-stage shift register to selected inputs of said plurality of non-linear logic means; e. means for logically combining the string of data bits with the combined output of a selected one of said plurality of non-linear logic means to provide a partially encoded data bit signal; and f. shuffle means for sequentially receiving blocks of the partially encoded data bit signal and for programmably shuffling the data bit positions within each of the sequentially received blocks of data bits to provide a fully encoded data bit string.

Claim 7

The cryptic device according to claim 4 wherein said means for logically combining is an EXCLUSIVE-OR gate having one input connected to receive said string of serial data and another input connected to receive a combined output from a selected one of said plurality of non-linear logic means so as to provide as an output said partially encoded data bit signal.

Claim 8

The cryptic device according to claim 4 wherein said shuffle means is comprised of: a multiple stage shift register each stage of which has an input and an output terminal; and programming means for selectively connecting the input terminals of selected stages to the output terminals of selected stages so as to shuffle the data bit positions within each of the sequentially received blocks of data bits to provide said fully encoded data bit string.