Patent US4003016A successfully refreshed from Google Patents.
US4003016A
Expired / Lapsed
US
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Digital beamforming system
Assignee: United States Department of the Navy
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Filing: 1975-10-06
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Granted: 1977-01-11
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Expires: 1995-10-06
Abstract
Abstract Each ring of a two ring transducer array provides signals that are bandpad filtered and hard-clipped. These signals are sampled in parallel at a predetermined frequency. The sampled signals are conducted to Adder circuits with appropriate delays being applied to predetermined signals. By sequentially changing the signals having a delay inserted and those applied directly to the Adder a 360° azimuthal scan is provided in discrete angular steps. The sums of Adders of each ring are then combined. The system provides scans in the horizontal direction and at predetermined depression/elevation angles.
Inventors
- 👤 Winslow Rodeck Remley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:52
CPC Classifications
G; G10; G10K; G10K11/00; G10K11/18; G10K11/26; G10K11/34; G10K11/341; G10K11/346; H; H04; H04R; H04R2201/00; H04R2201/40; H04R2201/401
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
173 words
A signal processing system comprising: a plurality of transducers for providing a plurality of respective output signals, said transducers arranged to form an array exhibiting ring symmetry; a plurality of filtering and clipping means to filter and clip respective transducer output signals; a multiplexer having a plurality of input terminals, each of said multiplexer input terminals connected to a respective member of said plurality of filtering and clipping means for receiving filtered and clipped signals, said multiplexer having a plurality of output terminals that is less in number than said input terminals, each of said output terminals adapted for sequentially providing said filtered and clipped signals simultaneously at predetermined intervals; at least one pair of delay lines connected to respective members of a pair of selected multiplexer output terminals, said pair of delay lines adapted to delay received signals for a simultaneous predetermined period of time; and an adder connected to said pair of delay lines for receiving the delayed signals and connected directly to a second pair of selected multiplexer output terminals.
Claim 2
Dependent Claim
173 words
A signal processing system comprising: a plurality of transducers for providing a plurality of respective output signals, said transducers arranged to form an array exhibiting ring symmetry; a plurality of filtering and clipping means to filter and clip respective transducer output signals; a multiplexer having a plurality of input terminals, each of said multiplexer input terminals connected to a respective member of said plurality of filtering and clipping means for receiving filtered and clipped signals, said multiplexer having a plurality of output terminals that is less in number than said input terminals, each of said output terminals adapted for sequentially providing said filtered and clipped signals simultaneously at predetermined intervals; at least one pair of delay lines connected to respective members of a pair of selected multiplexer output terminals, said pair of delay lines adapted to delay received signals for a simultaneous predetermined period of time; and an adder connected to said pair of delay lines for receiving the delayed signals and connected directly to a second pair of selected multiplexer output terminals.
Claim 3
Dependent Claim
18 words
A signal processing system according to claim 1 wherein said delay lines comprise a plurality of shift registers.
Claim 4
Dependent Claim
251 words
A signal processing system comprising: a plurality of transducer rings with each of said rings including a transducer array exhibiting ring symmetry and having an identical number of transducer elements; a plurality of filtering and clipping means adapted to filter and clip respective transducer element output signals; a plurality of multiplexer units, each of said units having a plurality of input terminals connected to a respective member of said plurality of filtering and clipping means for receiving filtered and clipped signals from the same transducer ring, each of said multiplexer units having a plurality of output terminals that is less in number than said input terminals, each of said output terminals adapted for sequentially providing said filtered and clipped signals at predetermined intervals; a plurality of delay lines connected to a first plurality of selected multiplexer output terminals of each of said multiplexer units, said delay lines adapted to delay each received signal for a plurality of predetermined time intervals; a first plurality of adders with each adder connected to one of said multiplexers and a plurality of said delay lines, so as to have each adder receive and add signals from a plurality of transducers on one of said plurality of transducer rings to form a signal indicative of a wavefront at a predetermined elevation angle received by the one of said plurality of transducer rings; and a second plurality of adders connected to said first plurality of adders so as to sum respective signals of the same elevation angle.
Claim 5
Dependent Claim
251 words
A signal processing system comprising: a plurality of transducer rings with each of said rings including a transducer array exhibiting ring symmetry and having an identical number of transducer elements; a plurality of filtering and clipping means adapted to filter and clip respective transducer element output signals; a plurality of multiplexer units, each of said units having a plurality of input terminals connected to a respective member of said plurality of filtering and clipping means for receiving filtered and clipped signals from the same transducer ring, each of said multiplexer units having a plurality of output terminals that is less in number than said input terminals, each of said output terminals adapted for sequentially providing said filtered and clipped signals at predetermined intervals; a plurality of delay lines connected to a first plurality of selected multiplexer output terminals of each of said multiplexer units, said delay lines adapted to delay each received signal for a plurality of predetermined time intervals; a first plurality of adders with each adder connected to one of said multiplexers and a plurality of said delay lines, so as to have each adder receive and add signals from a plurality of transducers on one of said plurality of transducer rings to form a signal indicative of a wavefront at a predetermined elevation angle received by the one of said plurality of transducer rings; and a second plurality of adders connected to said first plurality of adders so as to sum respective signals of the same elevation angle.
Claim 6
Dependent Claim
18 words
A signal processing system according to claim 3 wherein said delay lines comprise a plurality of shift registers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |