US4002991A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pilot signal extracting circuitry
Assignee: Nippon Gakki Co Ltd
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Filing: 1976-01-02
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Granted: 1977-01-11
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Expires: 1996-01-02
Abstract
Abstract A pilot signal extracting circuitry designed to extract, from a composite signal consisting of plural signals modulated by a suppressed carrier modulation system, a pilot signal for controlling the generation of a carrierwave which is used for the demodulation of the composite signal. The pilot signal extracting circuitry comprises: a circuit for generating a signal synchronous with the pilot signal contained in the composite signal; a synchronous detector circuit for receiving, as the inputs, the composite signal and the synchronous signal, and for thereby generating a DC voltage having an value proportional to the level of the pilot signal contained in the composite signal; and a pulse-forming circuit for receiving, as the inputs, the DC voltage and the synchronous signal, and for thereby forming a pulse, i.e. the extracted pilot signal, which is synchronous with the synchronous signal and which has an amplitude proportional to the value of the DC voltage. Thus is obtained a stable pilot signal having a correct frequency and phase without distortion or fluctuation and having a magnitude well proportional to the received pilot signal level, which pilot signal is very suitable for demodulation.
Inventors
- 👤 Minoru Ogita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:16
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H04B1/1653; H03; H03D; H03D1/00; H03D1/22; H03D1/2209; H03D1/2236; H03L; H03L7/00; H03L7/06
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
144 words
A pilot signal extracting circuitry for extracting a pilot signal from a composite signal consisting of plural signals modulated by a suppressed carrier modulation system, comprising: a synchronous signal generating circuit for receiving said composite signal and for thereby generating a synchronous signal which is synchronous with the pilot signal contained in said composite signal; a synchronous detector circuit for receiving said synchronous signal and said composite signal and for thereby generating a DC voltage having a value proportional to the level of said pilot signal contained in said composite signal; and a pulse-forming circuit for receiving said synchronous signal and said DC voltage and for thereby forming a pulse which is synchronous with said synchronous signal and which has a magnitude proportional to the value of said DC voltage, said pulse formed by said pulse-forming circuit being used as an extracted pilot signal.
Claim 2
Dependent Claim
144 words
A pilot signal extracting circuitry for extracting a pilot signal from a composite signal consisting of plural signals modulated by a suppressed carrier modulation system, comprising: a synchronous signal generating circuit for receiving said composite signal and for thereby generating a synchronous signal which is synchronous with the pilot signal contained in said composite signal; a synchronous detector circuit for receiving said synchronous signal and said composite signal and for thereby generating a DC voltage having a value proportional to the level of said pilot signal contained in said composite signal; and a pulse-forming circuit for receiving said synchronous signal and said DC voltage and for thereby forming a pulse which is synchronous with said synchronous signal and which has a magnitude proportional to the value of said DC voltage, said pulse formed by said pulse-forming circuit being used as an extracted pilot signal.
Claim 3
Dependent Claim
42 words
A pilot signal extracting circuitry according to claim 1, in which: said synchronous signal generating circuit is a band-pass filter whose passing-frequency band has a center frequency thereof substantially equal to the frequency of said pilot signal contained in said composite signal.
Claim 4
Dependent Claim
21 words
A pilot signal extracting circuitry according to claim 1, in which: said synchronous signal generating circuit is a phase-locked loop circuit.
Claim 5
Dependent Claim
35 words
A pilot signal extracting circuitry according to claim 1, in which: said pulse-forming circuit is an analog gate, and the passing of said DC voltage through said analog gate is controlled by said synchronous signal.
Claim 6
Dependent Claim
43 words
A pilot signal extracting circuitry according to claim 4, in which: said analog gate has a transistor which is connected to a signal path for passing said DC voltage therethrough and which has a base electrode to which is applied said synchronous signal.
Claim 7
Dependent Claim
56 words
A pilot signal generating circuitry according to claim 1, in which: said synchronous detector circuit comprises: a transistor connected in parallel between a signal path for passing said composite signal therethrough and the ground of said circuitry, and an integration circuit for integrating the voltage appearing between the collector and the emitter electrodes of said transistor.
Claim 8
Dependent Claim
41 words
A pilot signal extracting circuitry according to claim 1, in which: said synchronous detector circuit comprises: a phase detector for receiving said composite signal and said synchronous signal, and an integration circuit for integrating the output signal of said phase detector.
Claim 9
Dependent Claim
36 words
A pilot signal extracting circuitry according to claim 1, in which: said pulse-forming circuit is a gain-controllable amplifier which amplifies said synchronous signal inputted thereto with an amplitude factor controlled by said DC voltage applied thereto.
Claim 10
Dependent Claim
128 words
A pilot signal extracting circuitry according to claim 8, in which: said gain-controllable amplifier comprises: a voltage divider including a variable impedance element for dividing said synchronous signal applied thereto, and a differential amplifier which receives said DC voltage and a DC component of the resultant signal of said synchronous signal after being divided by said voltage divider, and which thereby delivers an output voltage proportional to the voltage difference between said DC voltage and said DC component, said output voltage being applied to the control terminal of said variable impedance element as a control signal for controlling the impedance of said variable impedance and for thereby varying the dividing ratio of said voltage divider, and in which: said synchronous signal generating circuit is a phase-locked loop circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |