Telephone circuit to eliminate use of a hold button

Claim 2

A telephone circuit to eliminate use of a hold button comprising: a subset having a receiver and a transmitter for use by one party; a plurality of central office lines connected to outside parties; a plurality of internal lines connected to internal parties; first means to couple said receiver and said transmitter to a selected one of said central office lines to enable a first two-way conversation between said one party and a selected one of said outside parties, said first means including a first network coupled between said transmitter and said receiver to reduce sidetones in said receiver; second means to couple said receiver and said transmitter to a selected one of said internal lines to enable a second two-way conversation between said one party and a selected one of said internal parties, said second means including a second network coupled between said transmitter and said receiver to reduce sidetones in said receiver; and third means coupled between said first means and said second means, said third means having a first state to enable said first and second conversations to be carried on simultaneously and to prevent said selected one of said outside parties and said selected one of said internal parties from hearing each other and a second state to selectively enable said one party, said selected one of said outside parties and said selected one of said internal parties to be placed in a two-way conference.

Claim 3

A circuit according to claim 1, wherein said first means includes a line selector switch coupled to said plurality of central office lines to enable selection of said selected one of said central office lines, an impedance matching network coupled to said line selector switch, said impedance matching network having a transformer, a receiver isolation amplifier having at least one input coupled to one terminal of one winding of said transformer and its output coupled to said receiver, a transmitter isolation amplifier having at least one input coupled to said transmitter, a first resistor coupled between the other terminal of said one winding of said transformer and the output of said transmitter isolation amplifier, and said first network having a reference potential, and a second resistor coupled between a point on said one winding of said transformer intermediate said one and said other terminals of said one winding of said transformer and said reference potential.

Claim 4

A circuit according to claim 2, wherein each of said receiver isolation amplifier and said transmitter isolation amplifier includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.

Claim 5

A circuit according to claim 1, wherein said second means includes a line selector switch coupled to said plurality of internal lines to enable selection of said selected one of said internal lines, an impedance matching network coupled to said line selector swtich, through said third means said impedance matching network having a transformer a receiver isolation amplifier having at least one input coupled to one terminal of one winding of said transformer and its output coupled to said receiver, a transmitter isolation amplifier having at least one input coupled to said transmitter, a first resistor coupled between the other terminal of said one winding of said transformer and the output of said transmitter isolation amplifier, and said second network having a reference potential, and a second resistor coupled between a point on said one winding of said transformer intermediate said one and said other terminals of said one winding of said transformer and said reference potential.

Claim 6

A circuit according to claim 4, wherein each of said receiver isolation amplifier and said transmitter isolation amplifier includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.

Claim 7

A circuit according to claim 1, wherein said third means includes a source of direct current voltage, a momentary action switch coupled to said source, a D-type flip flop having a D terminal, a Q terminal and a clock terminal, said clock terminal being coupled to said switch, and a relay coupled to said D and Q terminals, said relay preventing connection of said selected one of said central office lines to said selected one of said internal lines during said first state of said third means and interconnecting said selected one of said central office lines and said selected one of said internal lines when the output signal of said D and Q terminal is high during said second state of said third means.

Claim 8

A circuit according to claim 1, wherein said first means includes a first line selector switch coupled to said plurality of central office lines to enable selection of said selected one of said central office lines, a first impedance matching network coupled to said first line selector switch, said first impedance matching network having a first transformer, a first receiver isolation amplifier having at least one input coupled to one terminal of one winding of said first transformer and its output coupled to said receiver, a first transmitter isolation amplifier having at least one input coupled to said transmitter, a first resistor coupled between the other terminal of said one winding of said first transformer and the output of said first transmitter isolation amplifier, and said first network includes a reference potential, and a second resistor coupled between a point on said one winding of said first transformer intermediate said one and said other terminals of said one winding of said first transformer and said reference potential; and said second means includes a second line selector switch coupled to said plurality of internal lines to enable selection of said selected one of said internal lines, a second impedance matching network coupled to said second line selector switch, through said third means said second impedance matching network including a second transformer, a second receiver isolation amplifier having at least one input coupled to one terminal of one winding of said second transformer and its output coupled to said receiver, a second transmitter isolation amplifier having at least one input coupled to said transmitter, a third resistor coupled between the other terminal of said one winding of said second transformer and the output of said second transmitter isolation amplifier, and said second network having a fourth resistor coupled between a point on said one winding of said second transformer intermediate said one and said other terminals of said one winding of said second transformer and said reference potential.

Claim 9

A circuit according to claim 7, wherein each of said first and second receiver isolation amplifiers and said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.

Claim 10

A circuit according to claim 7, wherein said third means is connected between the output of said first and second line selector switches and to the input of said second impedance matching network.

Claim 11

A circuit according to claim 9, wherein said third means includes a source of direct current voltage, a momentary action switch coupled to said source, a D-type flip flop having a D terminal, a Q terminal and a clock terminal, said clock terminal being coupled to said momentary action switch, and a relay coupled to said D and Q terminals, said relay preventing connection of said selected one of said central office lines to said selected one of said internal lines during said first state of said third means and interconnecting said selected one of said central office lines to said selected one of said internal lines when the output signal of said D and Q terminals is high during said second state of said third means.

Claim 12

A circuit according to claim 10, wherein each of said first and second receiver isolation amplifiers and said first and second transmitter isolation amplifiers includes an operational amplifier with differential inputs to reduce the amplification of a common mode signal.