US4001701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for combining pulse trains
Assignee: INVALCO Inc
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Filing: 1975-09-25
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Granted: 1977-01-04
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Expires: 1995-09-25
Abstract
Abstract An electric circuit with a plurality of inputs, each input receiving a train of pulses. Each pulse of each train sets a latch of cross-coupled logic gates to an output of logic 1. A clock generating regular voltage pulses is connected in parallel to the latches so as to reset the output of each gate to logic 0 in series with each other. The plurality of outputs from the latches is passed through a common gate to form the output train of pulses as an addition of the plural inputs.
Inventors
- 👤 John B. Rosso
- 👤 Sheyrl Wayne Garrett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:30
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; G; G06; G06F; G06F7/00; G06F7/60; G06F7/605
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
207 words
A circuit arranged to respond to a plurality of voltage pulse trains and generate a single voltage pulse train which is an addition of the plurality of trains, including; a first circuit section connected to a first of the input pulse trains, including, a. a pair of logic gate circuits connected as a cross coupled latch and connected to receive the pulses of the input to the section and generate an output logic 1, b. a connection between the output of an independent, stable source of voltage pulses and the cross coupled latch through which a first of the edges of the pulses shifts the latch output to logic 0. c. and a resistance divider circuit means capacitively connected to said latch and responding to only the shift in the latch output to logic 0 to generate a voltage pulse in the output of the circuit; and a second circuit section connected to a second of the input pulse trains which generates a voltage pulse in the output of the circuit with the second of the edges of the pulses of the stable source of voltage pulses, whereby the differential source pulses generates a pulse train output of the circuit from the plurality of input pulse trains.
Claim 2
Dependent Claim
207 words
A circuit arranged to respond to a plurality of voltage pulse trains and generate a single voltage pulse train which is an addition of the plurality of trains, including; a first circuit section connected to a first of the input pulse trains, including, a. a pair of logic gate circuits connected as a cross coupled latch and connected to receive the pulses of the input to the section and generate an output logic 1, b. a connection between the output of an independent, stable source of voltage pulses and the cross coupled latch through which a first of the edges of the pulses shifts the latch output to logic 0. c. and a resistance divider circuit means capacitively connected to said latch and responding to only the shift in the latch output to logic 0 to generate a voltage pulse in the output of the circuit; and a second circuit section connected to a second of the input pulse trains which generates a voltage pulse in the output of the circuit with the second of the edges of the pulses of the stable source of voltage pulses, whereby the differential source pulses generates a pulse train output of the circuit from the plurality of input pulse trains.
Claim 3
Dependent Claim
139 words
A circuit connected to a plurality of voltage pulse trains, including; a section for receiving each pulse train, each section including; a. a pair of logic gate circuits connected to form a cross-coupled latch and receiving the pulse train to the section as one of two inputs, b. a resistance divider circuit means capacitively connected to the output of the latch so as to generate an output voltage pulse as the latch output shifts in a predetermined direction, c. and a source of independent stable, cyclic voltage pulses connected to the latch as the other of the two inputs, a selected edge of each pulse shifting the latch output in the predetermined direction; whereby the output voltage pulses from the circuit means of each section is sequentially formed into an output of the circuit as a single pulse train.
Claim 4
Dependent Claim
139 words
A circuit connected to a plurality of voltage pulse trains, including; a section for receiving each pulse train, each section including; a. a pair of logic gate circuits connected to form a cross-coupled latch and receiving the pulse train to the section as one of two inputs, b. a resistance divider circuit means capacitively connected to the output of the latch so as to generate an output voltage pulse as the latch output shifts in a predetermined direction, c. and a source of independent stable, cyclic voltage pulses connected to the latch as the other of the two inputs, a selected edge of each pulse shifting the latch output in the predetermined direction; whereby the output voltage pulses from the circuit means of each section is sequentially formed into an output of the circuit as a single pulse train.
Claim 5
Dependent Claim
49 words
The circuit of claim 2 in which the pair of logic gate circuits are NAND gates which receive each pulse to their section for generation of an output logic 1 and the circuit means generates its output voltage pulse as the logic 1 output is shifted to logic 0.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-04 | 1980-07-05 | 1981-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-04 | 1984-07-05 | 1985-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-04 | 1988-07-05 | 1989-01-04 | $7700.00 | Window Closed / Lapsed |