Analog timer including controllable operate-recovery time constants

Claim 2

An analog timer of the type employed to generate an output pulse signal a predetermined time interval after application of an input pulse signal including an integrator circuit having a predetermined linear integration rate for developing a signal which is the mathematical integral of the input pulse signal and a comparator circuit responsive to the difference between a signal developed by the integrator and a reference signal for generating the delayed output pulse, wherein the improvement comprises: controllable impedance means responsive to the comparator output and the applied input signal for changing the integration rate including a plurality of impedance elements having predetermined component values and means responsive to said applied input signal for connecting said impedance elements in predetermined circuit relationships; and means connected in circuit with said connecting means and being responsive to the comparator output for inhibiting said connection of said impedance elements during intervals that the comparator output is of predetermined polarity, wherein a change in the integrator integration rate is inhibited during said intervals.

Claim 3

An analog timer as defined in claim 1 wherein said impedance elements include at least first and second resistor means, said integrator includes a differential amplifier having an inverting input, noninverting input and output, said noninverting input being connected to a reference potential point, capacitor means being connected between said inverting input and said output, said comparator being connected to sense a signal developed at said inverting input of said amplifier, said at least first and second resistor means being connected in circuit relationship between an input of said timer and said inverting input of said amplifier, said connecting means including switching means connected in circuit with said first resistor means and being responsive to the instantaneous polarities of the input signal applied to said timer input controllably to connect said first resistor means in circuit with said inverting input during intervals that the input signal is of a prescribed polarity, and wherein said inhibiting means in connected in predetermined circuit relationship with said first resistor means and said switching means and is responsive to instantaneous polarities of the comparator output signal to inhibit said switching means from connecting said first resistor means in circuit with said inverting input during intervals that the comparator output is of a prescribed polarity.

Claim 4

An analog timer as defined in claim 2 wherein said switching means is a first diode poled to conduct current when said input signal is of said prescribed polarity and wherein said inhibiting means is a second diode connected to a circuit junction between said first resistor means and said first diode and is poled to clamp said circuit junction to a predetermined potential when the output signal from said comparator is of said prescribed polarity, thereby inhibiting conduction through said first diode.

Claim 5

An analog timer of the type employed to generate an output pulse signal a predetermined time interval after application of an input pulse signal which includes an integrator circuit having a predetermined linear integration rate for developing a signal which is the mathematical integral of the input pulse signal, and a comparator circuit responsive to a difference between a signal developed by the integrator and a reference signal for generating the delayed output pulse, wherein the improvement comprises: means connected in circuit with the integrator and being responsive to the output signal developed by the comparator for controlling changes in the integration rate of the integrator including controllable impedance means responsive to the applied input pulse signal and the comparator output signal for controllably changing the integrator integration rate in accordance with prescribed relationships of the applied input pulse signal and comparator output signal.

Claim 6

An analog timer of the type employed to generate an output pulse signal a predetermined time interval after application of an input pulse signal which includes an integrator circuit having a predetermined linear integration rate for developing a signal which is the mathematical integral of the input pulse signal, and a comparator circuit responsive to a difference between a signal developed by the integrator and a reference signal for generating the delayed output pulse, wherein the improvement comprises: means connected in circuit with the integrator and being responsive to the output signal developed by the comparator for controlling changes in the integration rate of the integrator including controllable impedance means responsive to the applied input pulse signal and the comparator output signal for controllably changing the integrator integration rate in accordance with prescribed relationships of the applied input pulse signal and comparator output signal.

Claim 7

An analog timer as defined in claim 4 wherein said controlling means includes means for inhibiting a change in the integrator integration rate during intervals that the output from the comparator has a predetermined polarity.

Claim 8

An analog timer of the type employed to generate an output pulse signal a predetermined time interval after application of an input pulse signal which includes an integrator circuit having a predetermined linear integration rate which is the mathematical integral of the applied input pulse signal and a comparator circuit responsive to the difference between a signal developed by the integrator and a reference signal for generating the delayed output pulse wherein the improvement comprises, controllable impedance means in circuit with the integrator and being responsive to the applied input signal and the comparator output signal including a plurality of impedance elements connectable in predetermined circuit relationships to obtain corresponding integration rates, and means responsive to the applied input signal and the comparator output signal for effecting connection of said elements in accordance with prescribed relationships between the input and output signals to obtain changes in the integrator integration rate.

Claim 9

An analog timer of the type employed to generate an output pulse signal a predetermined time interval after application of an input pulse signal which includes an integrator circuit having a predetermined linear integration rate which is the mathematical integral of the applied input pulse signal and a comparator circuit responsive to the difference between a signal developed by the integrator and a reference signal for generating the delayed output pulse wherein the improvement comprises, controllable impedance means in circuit with the integrator and being responsive to the applied input signal and the comparator output signal including a plurality of impedance elements connectable in predetermined circuit relationships to obtain corresponding integration rates, and means responsive to the applied input signal and the comparator output signal for effecting connection of said elements in accordance with prescribed relationships between the input and output signals to obtain changes in the integrator integration rate.

Claim 10

An analog timer as defined in claim 6 wherein said integrator includes a differential amplifier having an inverting input, noninverting input and output, said noninverting input being connected to a reference potential point, capacitor means connected between said inverting input and said amplifier output, said comparator means being connected to sense a potential developed at said inverting input, said impedance elements including at least first, second and third resistor means being connected in circuit relationship with an input of said timer and said inverting input of said amplifier, said connecting means including first and second switching means connected in circuit with said first and second resistor means, respectively, and being responsive to instantaneous polarities of an input signal applied to said timer input controllably to connect said first and second resistor means in circuit between said timer input and said inverting input during intervals that the polarity of said input signal is of first and second polarities, respectively, first inhibiting means being connected in circuit relationship with said first resistor means and said first switching means and being responsive to the comparator output signal for inhibiting said first switching means from connected said first resistor means in circuit with said inverting input during intervals that the comparator output is of a first prescribed polarity and second inhibiting means being connected in circuit relationship with said second resistor means and said second switching means and being responsive to the comparator output signal for inhibiting said second switching means from connecting said second resistor means in circuit with said inverting input during intervals that the comparator output signal is of a second prescribed polarity.

Claim 11

An analog timer as defined in claim 7 wherein said first and second switching means are diodes poled to conduct current during intervals that said input signal is of said first and second polarities, respectively, and wherein said first and second inhibiting means are diodes poled to conduct current when the comparator output signal is of said first and second prescribed polarities, respectively, wherein said switching means and said inhibiting means respond to said input signal and said comparator output signal effectively to change the integration rate of the integrator in accordance with prescribed relationships between the polarities of said input signal and said comparator output.