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US4001604A Expired / Lapsed US ⏱️ 0.0 years remaining

Peak value detector

Assignee: United States Department of the Army
•
Filing: 1975-04-25
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Granted: 1977-01-04
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Expires: 1995-04-25
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Abstract

Abstract A circuit for detecting peaks in a time-variant signal, comprising a track-hold unit having a first mode for tracking the time-variant signal, and a second mode for storing instantaneous peak values. The track-hold unit is controlled by a comparator which samples the time-variant signal and stored peak; logic output of the comparator is applied to the track-hold unit to direct it into its first or second modes in accordance with the relative values of the sampled signals.

Inventors

  • 👤 Jack G. Parks
  • 👤 Gordon J. McInnes

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 00:10
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532; H03M; H03M1/00; H03M1/12; H03M1/124

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 276 words
A circuit for detecting peaks in a time-variant analog signal and converting same to digital form, comprising: a track-hold unit having an input (16) adapted to receive the time-variant signal, a signal storage means (18), a bistable gated switch (14), having a gate terminal, for alternately conducting the time-variant signal to the storage means or isolating the storage means from the time-variant signal, and output terminal (19) continuously connected to the storage means for delivering the stored signal; a comparator for comparing the time-variant signal and stored signal, said comparator having a first input terminal (24) connected to said track-hold unit input terminal (16), a second input terminal (26) connected to said track-hold unit output terminal (19), a first output terminal producing a first logic output signal (Q) when the time-variant signal exceeds the stored signal, and producing at a second output terminal a second logic output signal (Q) when the stored signal equals or exceeds the time-variant signal; circuit means (34a and 34b) responsive to said first logic output signal for applying said first logic signal to the gate terminal of said bistable switch, whereby said switch (14) is in its conducting state only when the time-variant signal exceeds the stored signal; a converter (38) for converting the stored time-variant signal at said track-hold unit output (19) to digital form; said converter having convert-control circuitry (50, 52, 54); an additional circuit means (44 and 48) coupled to said comparator second output terminal for applying said second logic output signal (Q) to said convert control circuitry whereby the converter is put into the convert mode only when the stored signal equals or exceeds the time-variant signal.
Claim 2
Dependent Claim 276 words
A circuit for detecting peaks in a time-variant analog signal and converting same to digital form, comprising: a track-hold unit having an input (16) adapted to receive the time-variant signal, a signal storage means (18), a bistable gated switch (14), having a gate terminal, for alternately conducting the time-variant signal to the storage means or isolating the storage means from the time-variant signal, and output terminal (19) continuously connected to the storage means for delivering the stored signal; a comparator for comparing the time-variant signal and stored signal, said comparator having a first input terminal (24) connected to said track-hold unit input terminal (16), a second input terminal (26) connected to said track-hold unit output terminal (19), a first output terminal producing a first logic output signal (Q) when the time-variant signal exceeds the stored signal, and producing at a second output terminal a second logic output signal (Q) when the stored signal equals or exceeds the time-variant signal; circuit means (34a and 34b) responsive to said first logic output signal for applying said first logic signal to the gate terminal of said bistable switch, whereby said switch (14) is in its conducting state only when the time-variant signal exceeds the stored signal; a converter (38) for converting the stored time-variant signal at said track-hold unit output (19) to digital form; said converter having convert-control circuitry (50, 52, 54); an additional circuit means (44 and 48) coupled to said comparator second output terminal for applying said second logic output signal (Q) to said convert control circuitry whereby the converter is put into the convert mode only when the stored signal equals or exceeds the time-variant signal.
Claim 3
Dependent Claim 31 words
The circuit of claim 1: and further comprising reset pulse means (60, 62) for temporarily directing the bistable switch into its conducting state irrespective of the nature of the comparator output.
Claim 4
Dependent Claim 46 words
The circuit of claim 2: the reset pulse means comprising a monostable multivibrator, and an OR gate; the OR gate responsive to inputs received from the multivibrator and said comparator first logic output terminal, the OR gate delivering its output to the gate of switch 14.
Claim 5
Dependent Claim 51 words
The circuit of claim 1: the combination further comprising means (40, 42) for translating said second logic output signal into discrete pulses; and a pulse counter (46) delivering an output signal to the aforementioned convert control circuitry after it has received a predetermined number of input pulses from the translating means.
Claim 6
Dependent Claim 32 words
The circuit of claim 4: the translating means comprising a clock pulse means (42) and an AND gate (40) receiving inputs from the clock pulse means and said comparator second output terminal.

References Cited (Backward Citations)

US3474259A Cited
US3521141A Cited
US3839680A Cited
US3891930A Cited
US3784921A Cited
US3820033A Cited
US3882489A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-01-04 1980-07-05 1981-01-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-01-04 1984-07-05 1985-01-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-01-04 1988-07-05 1989-01-04 $7700.00 Window Closed / Lapsed

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