US3820033A
Expired / Lapsed
US
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Mos-fet sample and hold system for digitizing high frequency signals
Assignee: Tektronix Inc
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Filing: 1973-05-16
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Granted: 1974-06-25
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Expires: 1993-05-16
Abstract
Abstract A MOS-FET sample and hold circuit to eliminate spike noise and offset voltage errors having single or difference sampling is provided.
Inventors
- 👤 H Iwata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:14
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026; H; H03; H03M; H03M1/00; H03M1/12; H03M1/124
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
196 words
A high speed sample and hold system comprising: input signal first amplifying means for amplifying input signals; switch means for switching said amplified signals and supplying output signals therefrom; second amplifier means for amplifying said output signals and supplying second output signals therefrom; sampling means for receiving said second output signals and a control signal for supplying sampled output voltages therefrom; first memorizing means to memorize said sampled output voltages and supplying said memorized voltages therefrom; third amplifying means for receiving said memorized voltages and supplying amplified voltages therefrom; fourth amplifying means for receiving said amplified voltages and supplying drive voltage therefrom wherein said means comprise second switch means for switching said amplified voltages, means for memorizing said switched amplified voltages, and means for providing said drive voltage; fifth amplifying means for receiving said amplified voltages and supplying drive voltage therefrom wherein said means comprise third switch means for switching said amplified voltages, means for memorizing said switched amplified voltages, and means for providing said drive voltage; and sixth amplifying means for receiving said drive voltages and supplying sampled output voltages therefrom wherein said output voltage is proportional to the substraction of said input drive voltages.
Claim 2
Dependent Claim
196 words
A high speed sample and hold system comprising: input signal first amplifying means for amplifying input signals; switch means for switching said amplified signals and supplying output signals therefrom; second amplifier means for amplifying said output signals and supplying second output signals therefrom; sampling means for receiving said second output signals and a control signal for supplying sampled output voltages therefrom; first memorizing means to memorize said sampled output voltages and supplying said memorized voltages therefrom; third amplifying means for receiving said memorized voltages and supplying amplified voltages therefrom; fourth amplifying means for receiving said amplified voltages and supplying drive voltage therefrom wherein said means comprise second switch means for switching said amplified voltages, means for memorizing said switched amplified voltages, and means for providing said drive voltage; fifth amplifying means for receiving said amplified voltages and supplying drive voltage therefrom wherein said means comprise third switch means for switching said amplified voltages, means for memorizing said switched amplified voltages, and means for providing said drive voltage; and sixth amplifying means for receiving said drive voltages and supplying sampled output voltages therefrom wherein said output voltage is proportional to the substraction of said input drive voltages.
Claim 3
Dependent Claim
25 words
The high speed sample and hold system according to claim 1 wherein said first, second, and third amplifying means defines high impedance, high frequency amplifiers.
Claim 4
Dependent Claim
29 words
The first, second, and third amplifiers according to claim 2 wherein said high impedance, high frequency amplifiers consists of at least one field effect transistor and one bipolar transistor.
Claim 5
Dependent Claim
39 words
The high speed sampling system according to claim 1 wherein said sampling means is an active device defining a field effect semiconductor having as a portion thereof a source electrode, a drain electrode, an insulated gate, and a substrate.
Claim 6
Dependent Claim
15 words
The field effect semiconductor according to claim 4 wherein said active device defines a MOS-FET.
Claim 7
Dependent Claim
21 words
The high speed sampling system according to claim 1 wherein said first, second, and third memorizing means defines an impedance means.
Claim 8
Dependent Claim
37 words
The memorizing means according to claim 6 wherein said impedance means defines a capacitor. 8 The high speed sampling system according to claim 1 wherein said first, second, and third switching means defines an electronic switching means.
Claim 9
Dependent Claim
17 words
The switching means according to claim 8 wherein said electronic switching means defines a field effect transistor.
Claim 10
Dependent Claim
16 words
The switching means according to claim 8 wherein said electronic switching means defines a bipolar transistor.
Claim 11
Dependent Claim
21 words
The switching means according to claim 8 wherein said electronic switching means defines a field effect transistor and a bipolar transistor.
Claim 12
Dependent Claim
21 words
The high speed sampling system according to claim 1 wherein said fourth, fifth, and sixth amplifying means defines high gain amplifiers.
Claim 13
Dependent Claim
19 words
The fourth, fifth and sixth amplifying means according to claim 12 wherein said high gain amplifiers defines differential amplifiers.
Claim 14
Independent Claim
79 words
The method of digitizing high frequency signals, comprising: applying first and second signals to first and second input terminals respectively; sampling said first signal or a reference signal alternately in response to said second signal; memorizing said sampled first signal in a first memorizing means; memorizing said sampled reference signal in a second memorizing means; amplifying thE difference betweeen said memorized reference signals; and applying said amplified difference to means for displaying said amplified difference in a digital form.
Claim 15
Independent Claim
79 words
The method of digitizing high frequency signals, comprising: applying first and second signals to first and second input terminals respectively; sampling said first signal or a reference signal alternately in response to said second signal; memorizing said sampled first signal in a first memorizing means; memorizing said sampled reference signal in a second memorizing means; amplifying thE difference betweeen said memorized reference signals; and applying said amplified difference to means for displaying said amplified difference in a digital form.
Claim 16
Dependent Claim
46 words
The method according to claim 14 wherein sampling said first signal or a reference signal alternately in response to said second signal defines controllably operating a MOS-field effect transistor having as a portion thereof a source electrode, a drain electrode, an insulated gate, and a substrate.
Claim 17
Independent Claim
80 words
The method of digitizing high frequency signals, comprising: applying first and second signals to first and second input terminals respectively; sampling said first signal alternately in response to the state of said second signal; memorizing said sampled first signal alternately in first and second memorizing means in response to the state of said second signal; amplifying the difference between said alternately memorized first signal; and applying said amplified difference to means for displaying said amplified difference in a digital form.
Claim 18
Independent Claim
80 words
The method of digitizing high frequency signals, comprising: applying first and second signals to first and second input terminals respectively; sampling said first signal alternately in response to the state of said second signal; memorizing said sampled first signal alternately in first and second memorizing means in response to the state of said second signal; amplifying the difference between said alternately memorized first signal; and applying said amplified difference to means for displaying said amplified difference in a digital form.
Claim 19
Dependent Claim
45 words
The method according to claim 16 wherein sampling said first signal alternately in response to the state of said second signal defines controllably operating a Mos-field effect transistor having as a portion thereof a source electrode, a drain electrode, an insulated gate, and a substrate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |